Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-07
2004-06-08
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C257S306000
Reexamination Certificate
active
06746914
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of applying the damascene process as part of the creation of a MIM capacitor.
(2) Description of the Prior Art
The manufacturing of semiconductor devices frequently requires the creation of electrical components that collectively perform functions of data manipulation (logic functions) or functions of data retention (storage functions). Most semiconductor devices are devices that perform binary logic functions that are reflected by on or off-mode conditions of binary circuits. In addition, a number of applications use analog levels of voltages, the voltages having a range of values between a high limit and a low limit. Digital and analog methods of signal processing may reside side by side in the same semiconductor device or package.
It is therefore not uncommon to see a mixture of electrical components and functions, comprising semiconductor devices, resistors and capacitors. The majority of semiconductor components consists of transistors, gate electrodes and a variety of switching components for the performance of logic processing functions. Capacitors may form a basic component of analog circuits in for instance switched capacitor filters. Capacitors are further widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits.
A capacitor may be used as part of analog processing capabilities. In digital circuits, the capacitor is used to provide charge storage locations for individual bits of digital data that are stored in the digital Integrated Circuit (IC).
The conventional process of creating a capacitor in combination with the creation of a CMOS device is a relatively complex and therefore expensive process. This will further emphasize that the process of the invention, whereby a Metal-Insulator-Metal (MIM) capacitor is created that can be applied for mixed-mode applications, is a relatively simple and therefore cost effective method of creating a capacitor. The invention uses methods that are conventionally used to create damascene structures. The invention therefore incorporates damascene technology into the process of creating a MIM capacitor.
U.S. Pat. No. 6,143,601 (Sun) shows a MIM and dual damascene process.
U.S. Pat. No. 6,184,550 (Van Buskirk et al.) shows an N-C barrier layer for a MIM capacitor.
U.S. Pat. No. 6,180,976 (Roy) shows a MIM patterned but no SiN seal layer.
U.S. Pat. No. 6,130,102 (White, Jr. et al.), U.S. Pat. No. 6,124,199 (Gambino et al.), U.S. Pat. No. 6,117,747 (Shao et al.) and U.S. Pat. No. 6,037,216 (Liu et al.) are related patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a manufacturable method of creating Metal-Insulator-Metal capacitors.
Another objective of the invention is to apply damascene processes to create Metal-Insulator-Metal capacitors.
In accordance with the objectives of the invention a new method is provided for the creation of a MIM capacitor. The invention starts with a semiconductor surface that is provided with semiconductor devices over the surface thereof. A first copper damascene process is applied for the creation of a first and a second damascene copper interconnect plug through a first layer of dielectric deposited over the surface of the substrate, the upper or trench portion of the dual damascene interconnects are copper wires in the surface of the first layer of dielectric. Deposited over the surface of the first layer of dielectric are a first layer of tantalum (for the formation of a bottom plate of a capacitor) over which is deposited a first layer of silicon nitride (for the formation of a capacitor dielectric) over which is deposited a second layer of tantalum (for the formation of a top plate of a capacitor). A one time etch of the three deposited layers forms a sandwich of three layers overlying the first plug, the patterned and etched three layers form a MIM capacitor. The etch stops at the surface of the first layer of dielectric and on the surface of the second dual damascene copper plug. A second layer of silicon nitride is deposited followed by the deposition of a second layer of dielectric. Third and fourth dual damascene openings are created through the second layer of dielectric and the second layer of silicon nitride. The third dual damascene opening aligns with MIM capacitor. The fourth dual damascene opening aligns with the second dual damascene plug. The dual damascene openings created through the second layer of dielectric are filled with copper, creating an access plug contacting the top plate of the capacitor and an access plug contacting the second dual damascene access plug.
REFERENCES:
patent: 6037216 (2000-03-01), Liu et al.
patent: 6117747 (2000-09-01), Shao et al.
patent: 6124199 (2000-09-01), Gambino et al.
patent: 6130102 (2000-10-01), White, Jr. et al.
patent: 6143601 (2000-11-01), Sun
patent: 6166423 (2000-12-01), Gambino et al.
patent: 6180976 (2001-01-01), Roy
patent: 6184550 (2001-02-01), Van Buskirk et al.
patent: 6222219 (2001-04-01), Gambino et al.
patent: 6259128 (2001-07-01), Adler et al.
patent: 6313003 (2001-11-01), Chen
patent: 6410386 (2002-06-01), Hsue et al.
patent: 6429474 (2002-08-01), Gambino et al.
patent: 6452251 (2002-09-01), Bernstein et al.
patent: 6466427 (2002-10-01), Chen
patent: 6483142 (2002-11-01), Hsue et al.
patent: 6492226 (2002-12-01), Hsue et al.
patent: 6498364 (2002-12-01), Downey et al.
patent: 6504205 (2003-01-01), Hsue et al.
patent: 6512260 (2003-01-01), Hsue et al.
patent: 2002/0179950 (2002-12-01), Morimoto et al.
patent: 2002/0192919 (2002-12-01), Bothra
patent: 2003/0025143 (2003-02-01), Lin
patent: 2003/0030084 (2003-02-01), Moise et al.
patent: 2003/0064583 (2003-04-01), Kim et al.
Chu Sanford
Hwei Ng
Kai Shao
Chartered Semiconductor Manufacturing Ltd.
Le Thao X.
Pham Long
Pike Rosemary L. S.
Saile George O.
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