Metal salicide process employing ion metal plasma deposition

Details Metal salicide process employing ion metal plasma deposition Metal salicide process employing ion metal plasma deposition

1997-12-31

1999-10-12

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438592, 438685, 438686, H01L 21336

Patent

active

059666072

ABSTRACT:
A process for forming metal salicide layers on an MOS transistor structure that reduces the risk of forming metal silicide bridges between source/drain regions and a polysilicon gate. The process includes the use of a uni-directional ion metal plasma deposition step to deposit a metal layer on the surface of a MOS transistor structure such that the ratio of the metal layer thickness on the surface of a gate sidewall spacers to the metal layer thickness on the surface of a polysilicon gate is no greater than 0.2. The relatively thin metal layer on the surface of the gate sidewall spacer reduces the possibility of forming metal silicide defects.

REFERENCES:
patent: 5858849 (1999-01-01), Chen
Dixit, G. a. et al, Ion Metal Plasma (IMP) Deposited Titanium Liners for 0.25/0.18 .mu.m Multilevel Interconnections, IEEE pp. 357-360 (1996). no month.
Wolf, S. et al., Silicon Processing for the VLSI Era I,pp. 397-399, (Lattice Press 1986). no month.

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