Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-25
1999-05-18
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438682, 438683, 438585, 438592, H01L21/336
Patent
active
059045337
ABSTRACT:
A metal salicide-CMP-metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on gates, sources (drains), spacers, and field oxides. A first high-temperature process is executed to form a first metal salicide layer on gates and sources (drains). A first wet etching is then performed. A first dielectric layer is formed over the semiconductor substrate wherein the horizontal line of the first dielectric layer is above the first metal salicide layer located on gates. A first chemical mechanical polishing (CMP) is then executed until the first metal salicide layer on gates is reached. A second metal layer is formed on the first dielectric layer and on the first metal salicide layer that is located on gates. A second high-temperature process is executed in order to form a thicker second metal salicide layer on the gates. A second wet etching is then performed. A second dielectric layer is formed over the semiconductor substrate. A second chemical mechanical polishing (CMP) is then executed. Finally, shallow contact windows and deep contact windows on gates and sources (drains) respectively are formed.
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Gurley Lynne A.
Niebling John F.
Winbond Electronics Corp.
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