Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-05
2003-01-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S106000
Reexamination Certificate
active
06511901
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and more specifically to metal redistribution layers.
BACKGROUND ART
Modern IC applications typically have high I/O pinout requirements. However, high pinouts pose problems for traditional wire bonded or TAB IC packages. Wire bonding and TAB packaging require that the die bond pads be disposed about the periphery of the semiconductor die. While I/O counts have been on the rise to accommodate increased functionality, die sizes have remained somewhat unchanged because improvements in the processing technology continue to decrease device geometries. Consequently, there is a minimum bond pitch limit with wire bonding techniques.
The development of solder bump arrays has significantly increased the pinout capability of semiconductor dice by utilizing the surface area of the die itself to provide a field of bond sites. A key element of this pinout scheme is the use of a metal redistribution layer. This is an interconnect layer disposed atop a finished semiconductor die. Electrical connections from the interconnect layer are made to the underlying die bond pads which are typically disposed about the die periphery. The interconnects serve to redistribute the bond pads from the periphery over the surface area of the die, thus permitting higher I/O pinouts out of the die.
As pinout requirements continue to increase, there is a need to combine solder bumping methods with wire binding techniques to provide even greater pinout capability. However, the materials used for each approach are mutually exclusive. Materials suited for solder bumps have poor mechanical adhesion properties and are thus not suited for wire bonding. For example copper is a highly solderable material, but is a poor choice for wire bonding. The reason is that copper readily forms an oxide layer which exhibits poor bonding properties. While an ambient can be provided within which adequate bonding will take place, the cost of doing so is prohibitively expensive and so the process has never developed.
Similarly, materials which exhibit good wire bonding capability generally do not do well when soldered. For example, aluminum is a good material for bonding. However, the oxide layer which forms over aluminum must be removed in order to achieve a strong solder joint. Etchants for removing the oxide layer are extremely aggressive and tend to etch away portions of the underlying aluminum in addition to the oxide layer. While this overetch may be acceptable where bulk aluminum is used, it is a problem with thin film aluminum structures since there is very little aluminum to start with.
There is a need, therefore, for a redistribution metallization which can accommodate both solder bumping and wire bonding. It is desirable to have a process which integrates well with existing redistribution metallization methods and yet provide solder bumps and wire bond structures.
SUMMARY OF THE INVENTION
The redistribution metallization scheme of the present invention includes conventional solder bumps in addition to the presence of new wire bond pads which can serve to relocate the bond pads which exist on the semiconductor die. This improves the connectivity options for the device, especially in flip-chip applications.
Fabrication of the redistribution metallization in accordance with the invention includes depositing a passivation layer and forming openings to the underlying bond pads as needed. A trimetal layer is then blanket deposited atop the passivation layer and etched to form the necessary redistribution traces. At the same time additional wire bond pads are patterned as well. A second passivation is deposited and etched to expose areas atop the underlying metallization at location where solder bumps will be formed and at locations corresponding to the added wire bond pads. Next, solder bumps are formed. In one embodiment, a subsequent etch step is made to expose an underlying metal layer of the trimetal layer at the locations of the added wire bond pads.
REFERENCES:
patent: 4463059 (1984-07-01), Bhattacharya et al.
patent: 5455387 (1995-10-01), Hoffman et al.
patent: 5476815 (1995-12-01), Kawasumi
patent: 5554940 (1996-09-01), Hubacher
patent: 5719449 (1998-02-01), Strauss
patent: 5774340 (1998-06-01), Chang et al.
patent: 5844168 (1998-12-01), Schueller et al.
patent: 5977624 (1999-11-01), Heo et al.
patent: 6181569 (2001-01-01), Chakravorty
patent: 6232147 (2001-05-01), Matsuki et al.
patent: 1140940 (1998-02-01), None
Kovats Julius A.
Lam Ken M.
Atmel Corporation
Lattin Christopher
Niebling John F.
Schneck Thomas
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