Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-07-11
1999-03-02
Powell, William
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438654, 438655, 438675, 438680, 257751, 257753, 257757, H01L 2144
Patent
active
058770860
ABSTRACT:
The present invention is a process for planarization of substrate layers comprising apertures to form continuous, void-free contacts or vias in sub-half micron applications. A CVD silicon or metal silicide wetting layer is deposited onto the substrate layer comprising apertures to provide a conformal wetting layer for a PVD metal layer. The PVD metal layer is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The CVD layer diffuses into the PVD layer and the resulting conductive layer is substantially void-free. The planarization process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of vias and contacts occurs without the formation of an oxide layer over the CVD wetting layer.
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Applied Materials Inc.
Powell William
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