Metal oxide semiconductor field effect transistor for...

Details Metal oxide semiconductor field effect transistor for... Metal oxide semiconductor field effect transistor for...

2003-02-27

2004-10-19

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S290000, C438S649000, C438S664000, C438S682000, C438S683000

Reexamination Certificate

active

06806157

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor and a method for fabricating the same, and more particularly, to a metal oxide semiconductor field effect transistor for reducing the resistance between a source and a drain using silicide and a method for fabricating the same.
2. Description of the Related Art
FIG. 1
is a sectional view illustrating a conventional metal oxide semiconductor (MOS) field effect transistor. Referring to
FIG. 1
, a gate insulation layer
110
and a gate electrode
120
are sequentially stacked on a semiconductor substrate
100
. A spacer
150
is formed on each side of the gate electrode
120
. Deep source/drain regions
130
and source/drain extension regions
140
are formed in the semiconductor substrate
100
. A silicide layer
160
may be formed in a predetermined upper portion of each deep source/drain region
130
. The concentration of dopant in each source/drain extension region
140
is lower than that of the dopant in each deep source/drain region
130
. In addition, the thickness t
1
of the source/drain extension regions
140
is less than the thickness t
2
of the deep source/drain regions. Formation of the shallow source/drain extension regions
140
is important in restraining a hot carrier effect.
A matter of concern when reducing the size of a MOS field effect transistor due to a reduction in a design rule is the reduction of the length L of the gate electrode
120
. When the length L of the gate electrode
120
is reduced, it is necessary to reduce the size of the device in the vertical direction. Accordingly, it is also necessary to reduce the thickness t
1
of the source/drain extension regions
140
. However, when the thickness t
1
of the source/drain extension regions
140
is reduced, the serial resistance between the source and drain increases. To decrease the serial resistance between the source and the drain, the concentration of a dopant in each source/drain extension region
140
should be increased. However, in the case of boron (B) which is a P-type dopant or arsenic (As) which is an N-type dopant, the maximum density is about 3.0×10
20
-5.0×10
20
cm
−3
per unit volume, so there is a limitation in compensating for the increase in the resistance between the source and the drain.
The thickness of the gate spacer
150
as well as the length L of the gate electrode
120
should also be reduced to reduce the size of the device. However, when the thickness of the gate spacer
150
is reduced, the length of each source/drain extension region
140
is also reduced, so a resulting short channel effect may degrade the device characteristics. Accordingly, there is a limitation in reducing the lengths of the source/drain extension regions
140
. Moreover, the silicide layer
160
needs to have a predetermined or larger thickness in order to maintain low resistance in the silicide layer
160
. Due to the restraint on the reduction of the thickness of the silicide layer
160
, the thickness t
2
of each deep source/drain region
130
needs to be a predetermined or larger thickness.
In conclusion, resistance in a channel region formed between the source/drain extension regions
140
can be decreased by reducing the length L of the gate electrode, but it is not easy to reduce resistance in the source/drain extension regions
140
and the deep source/drain regions
130
due to restraint on the reduction of the lengths of the source/drain extension regions
140
and restraint on the reduction of the thicknesses of the deep source/drain regions
130
. Accordingly, even if the resistance in the channel region is reduced, resistance in the source/drain extension regions
140
and the deep source/drain regions
130
, the size ratios of which tend to increase in a device, is not reduced so that the resistance of the entire device rarely decreases.
SUMMARY OF THE INVENTION
To address the above limitations, it is a first object of the present invention to provide a metal oxide semiconductor (MOS) field effect transistor in which the resistance between a source and a drain is reduced using silicide.
It is a second object of the present invention to provide a method for fabricating the MOS field effect transistor by which the resistance between a source and a drain is reduced.
Accordingly, to achieve the first object of the invention, there is provided a MOS field effect transistor for reducing the resistance between a source and a drain. The MOS field effect transistor includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate. Deep source/drain regions are formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer portion having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer portion having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer portion in a predetermined upper portion of each of the source/drain extension regions.
It is preferable that each of the source/drain extension regions includes first source/drain extension regions, and second source/drain extension regions provided between the first source/drain extension regions and corresponding deep source regions. The second source/drain extension regions are preferably deeper than the first source/drain extension regions and shallower than the deep source/drain regions. The second silicide layer portion is preferably formed in the upper portion of each of the second source/drain extension regions.
The MOS field effect transistor may further includes spacers formed at the sidewalls of the gate insulation layer and the gate electrode. Here, it is preferable that the lengths of the first source/drain extension regions are defined by the thickness of the spacers.
The first and second silicide layer portions preferably form a step shape. The second silicide layer portion is preferably a cobalt silicide layer, a titanium silicide layer, a nickel silicide layer, a tungsten silicide layer, a platinum silicide layer, a hafnium silicide layer or a palladium silicide layer.
To achieve the second object of the invention, there is provided a method for fabricating a MOS field effect transistor having a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate. The method includes the steps of forming first source/drain extension regions in the semiconductor substrate by implanting impurity ions using the gate electrode as an ion-implantation mask, forming first spacers on the sidewalls of the gate electrode and the gate insulation layer, forming second source/drain extension regions deeper than the first source/drain extension regions by performing impurity ion-implantation using the first spacers and the gate electrode as an ion-implantation mask, forming second spacers on the outer walls of the first spacers, forming deep source/drain regions deeper than the second source/drain extension regions by performing impurity ion-implantation using the second spacers and the gate electrode as an ion-implantation mask, forming a first silicide layer portion having a first thickness in the upper portion of each of the deep source/drain regions, removing the second spacers to expose the surfaces of the second source/drain extension regions, and forming a second silicide layer portion having a second thickness in the upper portion of each of the exposed second source/drain extension regions.
Preferably, the second spacers are formed of a material that can be selectively etched with respect to the first spacers.
It is preferable that the step of forming the first silicide layer portion includes the s

Affiliated with

Also associated with

Rating

Metal oxide semiconductor field effect transistor for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Metal oxide semiconductor field effect transistor for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal oxide semiconductor field effect transistor for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3314362