Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-24
2001-01-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S291000, C438S302000, C438S174000, C438S194000, C438S217000, C438S478000, C438S510000, C438S525000, C438S527000
Reexamination Certificate
active
06180464
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a metal oxide semiconductor device on a semiconductor substrate. The invention has particular applicability in manufacturing metal oxide semiconductor devices having localized channel doping.
BACKGROUND ART
Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate an ion implanted channel region separating( the source/drain regions, and a thin gate oxide and a conductive gate formed above the channel region. A traditional approach to forming MOS devices comprises initially blanket doping the substrate with the intended channel implant before gate oxidation, forming the gate oxide and the gate, then counter-doping the source/drain regions and annealing to electrically activate the implants. However, this technique is problematic given the current demands for miniaturization and increased circuit density, which have led to a dramatic reduction in feature sizes. When feature sizes are scaled to below 1 &mgr;m, the traditional approach results in devices exhibiting undesirable short-channel effects, increased junction capacitance and mobility degradation (i.e. increased resistance) in the source/drain regions due to the presence of the unneeded heavy channel implant in the source/drain regions. Furthermore, during the annealing step, transient enhanced diffusion occurs, causing accelerated diffusion of source/drain dopants into the channel and out-diffusion of channel dopants to the source/drain regions, thereby decreasing the channel doping. To compensate, a higher initial channel doping concentration is necessary. However, raising the initial channel doping level further increases junction capacitance and degrades mobility in the source/drain regions.
As a result, the traditional approach is being largely replaced with newer methodologies. In one such technique, as illustrated in
FIG. 1A
a thin gate oxide
20
is first formed on a substrate
10
and a conductive gate
30
. typically of polysilicon, is formed over gate oxide
20
. Intended source/drain regions are then masked by masks
40
, and the channel region
50
is ion implanted through gate
30
with impurities
60
, as shown in FIG.
1
B. Thereafter, as shown in
FIG. 1C
, a heavy source/drain implant is performed to implant impurities
70
. The implants
60
,
70
are then electrically activated by heating, as by rapid thermal annealing (RTA).
Disadvantageously, bombardment of the silicon of substrate
10
with a high flux of ions during the heavy source/drain implant causes crystallographic defects
80
in silicon
10
(i.e., holes in the crystal structure). Such defects. in turn, cause unwanted diffusion of implants
60
,
70
, especially during the RTA process. During such diffusion, channel dopants
60
migrate under the source/drain junctions J, and defects
80
attract dopants
70
to fill holes in the silicon crystal structure, as shown in FIG.
1
D. The rise in doping level under the junctions J due the diffusion undesirably increases parasitic junction capacitance, thereby degrading device performance as by decreasing circuit speed. In addition, dopant migration from the channel region creates problems in controlling the threshold voltage of the finished device thereby lowering manufacturing yield.
There exists a need for methodology enabling the manufacture of semiconductor devices with channel doping localized under the gate, thereby reducing parasitic junction capacitance, improving device performance and increasing yield.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having localized channel doping under the gate without dopant migration under the source/drain junctions during processing, thereby avoiding device degradation.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming a polysilicon gate on a main surface of a semiconductor substrate; forming source/drain regions in the substrate having junctions with the substrate; heating to electrically activate the source/drain regions; ion implanting impurities at an acute angle into the substrate to form a lateral channel implant below the gate; and heating to electrically activate the lateral channel implant without substantially diffusing the lateral channel implant under the junctions.
Embodiments of the present invention include heating to activate the lateral channel implant at a temperature of about 800° C. or less. Advantageously, lateral channel implant activation can be implemented during subsequent silicidation of the gate electrode and/or source/drain regions.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description arc to be regarded as illustrative in nature, and not as restrictive.
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Krivokapic Zoran
Milic Ognjen
Advanced Micro Devices , Inc.
Hack Jonathan
Niebling John F.
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