Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-11-20
2007-11-20
Tran, Minh-Loan (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C438S508000
Reexamination Certificate
active
11116903
ABSTRACT:
An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
REFERENCES:
patent: 5565700 (1996-10-01), Chou et al.
patent: 2002/0132405 (2002-09-01), Disney
D.R. Disney et al., “A New 800V Lateral MOSFET with Dual Conduction Paths,” Proceedings of International Symposium on Power Semiconductor Devices and ICs, 2001, pp. 399-402.
Shibib Muhammed Ayman
Xu Shuming
Agere Systems Inc.
Tran Minh-Loan
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