Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-07
2004-06-01
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S430000, C257S307000, C257S534000
Reexamination Certificate
active
06743671
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an integrated capacitor and method of making the same. More particularly, the present invention relates to an electrically polar integrated capacitor, which has a substantially perfect matching property, suited for analog/digital (A/D) converters, digital/analog (D/A) converters, or switch cap circuits.
2. Description of the Prior Art
Passive components such as capacitors are extensively used in integrated circuit (IC) design for radio-frequency (RF) and mixed-signal applications, such as filters, resonant circuits, and bypassing. Due to trends toward higher-levels of integration to achieve a reduction in costs associated with IC fabrication processes, the IC industry continually strives to economize each step of the fabrication process to the greatest extent possible.
FIG. 1
is a typical view fragmentarily illustrating a high capacitance density integrated capacitor according to the prior art. As shown in
FIG. 1
, the prior art integrated capacitor
1
consists of a plurality of parallel-arranged vertical metal plates
100
and
120
. In
FIG. 1
, different shadings are used to distinguish the two terminals of the capacitor
1
, where the vertical plates
120
are electrically connected to a terminal A (or node A), and the vertical plates
100
are electrically connected to a terminal B (or node B). The vertical metal plates
100
and
120
are fabricated on a semiconductor substrate (not explicitly shown). Each of the vertical metal plates
100
consists of a plurality of metal slabs
10
a
,
10
b
,
10
c
, and
10
d
connected vertically using multiple via metal plates
120
consists of a plurality of metal slabs
12
a
,
12
b
,
12
c
, and
12
d
connected vertically using multiple via plugs
13
a
,
13
b
, and
13
c
. The vertical plate
100
and the vertical plate
120
are isolated from each other by a dielectric layer (not shown). Generally, metal slabs
10
a
,
10
b
,
10
c
, and
10
d
and metal slabs
12
a
,
12
b
,
12
c
, and
12
d
of the prior art integrated capacitor
1
are fabricated in an interconnect process known in the art. Unlike the traditional metal-on-metal (MOM) capacitors as known to those versed in the art, the prior art integrated capacitor
1
is fabricated without using extra photo-masks, thereby reducing production cost. Moreover, the prior art integrated capacitor
1
provides higher capacitance per unit area.
However, in operation, parasitic capacitance is produced at both the node A and the node B of the prior art integrated capacitor
1
between the vertical plate
120
and the substrate and between the vertical plate
100
and the substrate, hence rendering the prior art integrated capacitor
1
electrically non-polar. Please refer to
FIG. 2
with reference to FIG.
1
.
FIG. 2
is an equivalent circuit diagram of the prior art integrated capacitor
1
as set forth in FIG.
1
. As mentioned, the vertical plates
120
of the integrated capacitor
1
are electrically connected to the node A, and the vertical plates
100
of the integrated capacitor
1
are electrically connected to the node B. In operation, inter-plate capacitance C
in
, parasitic capacitance C
A
, and parasitic capacitance C
B
are generated between the node A and the node B. The parasitic capacitance C
A
is induced between lowest metal slab
10
a
of the vertical metal plate
100
and the electrically grounded semiconductor substrate. The parasitic capacitance C
B
is induced between lowest metal slab
12
a
of the vertical metal plate
120
and the electrically grounded semiconductor substrate. Due to the non-polar property presented by the prior art integrated capacitor
1
, the prior art integrated capacitor
1
is therefore not suited for the design of analog/digital (A/D) converters, digital/analog (D/A) converters, or switch cap circuits. Moreover, it is also known that the prior art integrated capacitors
1
suffer from a so-called “matching” problem. Referring to
FIG. 3
, an enlarged top view of a conventional finger-type integrated capacitor
30
is illustrated. As shown in
FIG. 3
, the prior art finger-type integrated capacitor
30
comprises a plurality of finger-interlaced like capacitor units
31
, each of which consists of a vertical metal plate
311
electrically connected to a node A and a vertical metal plate
312
electrically connected to a node B. The conventional finger-type integrated capacitor
30
is not “matching” because that the four sides (i.e., the a, b, c, d sides as specifically indicated) of the non-symmetric capacitor unit
31
are facing different surrounding environments respectively. One approach to solving this problem is using a dummy metal layout surrounding each of the capacitor units
31
. However, this approach cannot perfectly solve the above-mentioned problem and also wastes a great deal of valuable chip area.
SUMMARY OF INVENTION
Accordingly, the primary objective of the claimed invention is to provide an electrically polar integrated capacitor with a high capacitance density, which is perfectly “matching” and is suited for analog/digital (A/D) converters, digital/analog (D/A) converters, and switch cap circuits.
According to one preferred embodiment of the claimed invention, an integrated capacitor having an electrically polar property is disclosed. The integrated capacitor comprises a semiconductor substrate. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate consists of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the first vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A horizontal conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.
The foregoing has outlined, rather broadly, preferred and alternative features of the claimed invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the claimed invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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patent: 2002/0113292 (2002-08-01), Appel
patent: 2003/0003665 (2003-01-01), Nakagawa
patent: 2003/0062564 (2003-04-01), Kobayashi et al.
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Hu Man-Chun
Lin Wen-Chung
Ali Corporation
Fourson George
Hsu Winston
Toledo Fernando L.
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