Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-13
2004-09-14
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
06790721
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and, more particularly, to a fabrication method for forming storage cells in semiconductor devices, such as non-volatile flash memory devices.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory devices are currently used extensively through the electronics industry. One type of non-volatile semiconductor memory devices employs the use of floating gate memory cells that are able to retain and transfer charge through a variety of mechanisms which include avalanche injection, channel injection, tunneling, etc. A flash memory device is such a semiconductor device that utilizes a floating gate memory cell. As is the case with most semiconductors being fabricated, the industry continues to push for smaller devices that contain a larger number of memory cells than each previous generation. This is also the case for the flash memory device.
In a flash memory device, fabrication of the components that make up the floating gate transistor determines the ability of the device to be programmed and retain an electrical charge as well as the ability of the device to be reprogrammed by being erased (or the removal of the electrical charge). Flash memory cells comprising floating gate transistors are laid out in such a manner that a plurality of cells forms a memory array.
A device in the programmed state, i.e., charge stored on the floating gate, represents a stored “0” and a device in the non-programmed state, i.e., no charge stored on the floating gate, represents a stored “1.” Reading a device in the programmed state will cause the device to conduct heavily, while reading a device in the non-programmed state the device will not conduct. Each floating gate transistor in the array has a common source line and the common source line requires sophisticated fabrication techniques.
The present invention provides a floating gate device structure and method to fabricate a low resistant local interconnect self-aligned source that will provide enhanced operation of a flash memory cell device.
SUMMARY OF THE INVENTION
Exemplary implementations of the present invention comprise a flash memory device and processes therefor.
A first exemplary implementation of the present invention includes a flash memory device comprising a series of floating gate devices each having an implanted source electrode self-aligned to a respective gate electrode, the implanted source electrodes connected together by a conductively doped active area, and a metal interconnect running a major length of source electrodes that are serially connect by the self-aligned source, the metal interconnect making substantially continuous contact therebetween. The metal interconnect may comprise a tungsten-based metal, such as tungsten or tungsten/titanium.
A second exemplary implementation of the present invention includes process steps for forming a flash memory device on a semiconductor assembly.
A series of floating gate devices having their source electrodes connected together by a conductively doped active area is formed. The source electrodes of each device are self-aligned to their respective transistor gates of each said floating gate device. Then a nitride barrier layer is formed such that it overlies each transistor gate. Next, a planarized insulation layer is formed over said nitride barrier layer. Portions of the planarized insulation layer are removed while using the nitride barrier layer to self-align an interconnect via to underlying source electrodes. The nitride barrier layer is etched away, such as with an anisotropic dry etch, to expose the underlying self-aligned sources. A metal local interconnect is formed into the interconnect via. The metal interconnect runs the major length of the source electrodes, while making contact therebetween. It is optional to simultaneously form metal drain plugs for each floating gate device and self-aligning each metal drain plug to an underlying drain electrode. The metal interconnect and the metal drain plug may be formed from a tungsten-based metal, such as tungsten or tungsten/titanium.
REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 5731242 (1998-03-01), Parat et al.
patent: 5994733 (1999-11-01), Nishioka et al.
patent: 6080624 (2000-06-01), Kamiya et al.
patent: 6188115 (2001-02-01), Kamitani
patent: 6271087 (2001-08-01), Kinoshita et al.
patent: 2001/0024857 (2001-09-01), Parat et al.
patent: 2002/0039821 (2002-04-01), Wolstenholme
patent: 2003/0013253 (2003-01-01), Hurley
patent: 2003/0027390 (2003-02-01), Wolstenholme
patent: 2003/0064563 (2003-04-01), Wolstenholme
patent: 2003/0151080 (2003-08-01), Hurley et al.
patent: 2003/0206447 (2003-11-01), Tuan et al.
H. Watanabe et al., IEDM, 98 pp. 975-978.*
“Novel 0.44 &mgr;m2Ti-Salicide STI Cell Technology for High Density NOR Flash Memories and High Performance Embedded Application”, H. Watanabe et al., IEDM, 98 pp. 975-978.
“A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technology”, Kenichi Imamiya et al., IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999.
Coleman W. David
Micro)n Technology, Inc.
Nguyen Khiem
LandOfFree
Metal local interconnect self-aligned source flash cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal local interconnect self-aligned source flash cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal local interconnect self-aligned source flash cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3260275