Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-01-17
2004-06-15
Thomas, Tom (Department: 2815)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S393000, C438S239000
Reexamination Certificate
active
06750113
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention is integrated circuits with copper interconnect.
BACKGROUND OF THE INVENTION
In the course of forming the metallization of an integrated circuit, it is sometimes necessary to construct parallel plate capacitors. In the field of aluminum interconnections, such processes are well developed.
In the field of copper interconnect, however, development of a suitable process has proved to be unexpectedly difficult.
The potential hillocks and gouges in a copper metal surface can cause thinning and discontinuities in the active dielectric or in the capacitor plates, leading to early wear out and potential breakdown.
SUMMARY OF THE INVENTION
The invention relates to a parallel plate capacitor having a lower plate that does not include a layer of copper and does not extend over a lower copper interconnect in the area of the capacitor proper.
An optional feature of the invention is a composite lower plate having a material of lower resistivity, such as aluminum, covered by a top liner of material having a higher resistivity.
Another feature of the invention is the provision of a capacitor top plate that does not include copper and is smaller on all sides than the bottom plate.
Another feature of the invention is the deposition of an interlayer dielectric surrounding the capacitor that has a high material quality at least in the portion of the dielectric that is on the same level as the capacitor.
Another feature of the invention is the coverage of the capacitor stack by a material that provides lower etch rates during the etch of the interlayer dielectric to form contacts. The thickness of this material might be different for top and bottom plates.
Another feature of the invention is a multiple step process for opening contact apertures to the capacitor plates, in which a first step etches only partially through cap layers on the top plate and on lower interconnects while etching all the way through the cap above the bottom plate, after which the remaining portion of the cap layers is etched through.
Another feature is the layer of dielectric (i.e. ILD material) that is located between the hard dielectric cap on top of the underlying Cu metallization and the bottom plate of the capacitor. This layer protects that hard dielectric cap and the Cu of the underlying level during the formation of the bottom plate.
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Armacost Michael D.
Augustin Andreas K.
Friese Gerald R.
Heidenreich, III John E.
Hueckel Gary R.
Blecker Ira D.
Richards N. Drew
Thomas Tom
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