Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-11
2003-10-28
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S273000, C438S204000
Reexamination Certificate
active
06638824
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to field-effect transistors, in particular trench double-diffused metal-oxide-semiconductor (“DMOS”) transistors, and their method of manufacture.
DMOS transistors are a type of field-effect transistor (“FET”) that can be used as a power transistor, that is, a transistor that is used to switch or control relatively large amounts of electrical power compared to a transistor that might be used in a logic circuit application. Power transistors might operate between 5-30 volts, or higher, and might carry over several tenths of an amp to several amps of current. Power MOS FETs are designed to operate under conditions that would destroy conventional MOS FETs, or at least accelerate their failure. One design feature that can be incorporated into a DMOS FET to provide high-power handling capability is to increase the width of the gate of the FET. Using conventional terminology, the length of the gate relates to the distance between the drain and source, and the width relates to the run of the gate.
Generally speaking, the wider the gate, the higher the power-handling capability of the FET because the power-per-unit width of the gate is lower. However, increasing the gate width typically causes the gate on-resistance (“R
Gon
”) to undesirably increase. High R
Gon
can affect switching speeds in applications for power FETs, such as DC-to-DC converters.
One approach to reduce R
Gon
is to divide the gate of a single DMOS FET up into “cells”, each cell having a portion of the total gate width, and each of the sections of the gate within the cells being electrically coupled to a common voltage source, such as a bus bar, that is connected to the gate pad. However, even with techniques such as a cell configuration and gate voltage distribution bus bar, it is still desirable in some instances to further reduce R
Gon
. One way to accomplish this is to reduce the inherent resistivity of the material used as the gate conductor material.
Unfortunately, polysilicon, which has a relatively high resistivity, is typically used as the gate conductor material. Polysilicon is used because it can withstand the subsequent high-temperature processing of conventional DMOS device fabrication sequences, which form the channel and source regions with high-temperature diffusion processes. Many conventional MOS FETs can use materials other than polysilicon as the gate conductor because such high-temperature processing is not used in the fabrication sequence.
Accordingly, it is desirable to provide a DMOS transistor with lower R
Gon
and higher switching speed at a given operating point.
SUMMARY OF THE INVENTION
The present invention provides a DMOS transistor, including a method of manufacture, with a metal gate electrode. In a preferred embodiment, the metal gate electrode is self-aligned to the source regions after formation of the source regions. The metal gate DMOS transistor has improved gate resistance and lower gate tunnel leakage current than conventional polysilicon gate DMOS transistors. In a further embodiment, the chip area devoted to a gate bus is reduced in favor of additional active cell area, thus increasing the power-handling capability of a given die size without sacrificing switching speed.
The metal gate is self-aligned to the source regions, and a minimal but finite gate-source overlap is provided by the lateral diffusion of the source dopant in conjunction with the self-aligned feature of the gate. The metal gate material typically does not shrink after deposition onto the gate region to the same extent as polysilicon might shrink after deposition, thus fewer active region defects are generated by the metal gate, thus reducing gate leakage current, and improving device performance, lifetime, and reliability. The metal gate layer is formed after the high-temperature processing of the device is complete, particularly the channel and source diffusions.
In one embodiment, chemical-mechanical polishing (“CMP”) is used to fabricate a gate metal layer to a selected thickness.
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Chau Duc Q.
Mo Brian S.
Cao Phat X.
Doan Theresa T.
Fairchild Semiconductor Corporation
Townsend & Townsend & Crew LLP
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