Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-27
2000-03-14
Fahmy, Wael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438580, 438582, 438585, 438592, 438596, 438669, 438674, 438685, 438688, H01L 21336
Patent
active
060372338
ABSTRACT:
Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
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Yauh-Ching Liu, Gary K. Giust, Ruggero Castagnetti, and Subramanian Ramesh, "Silicide Encapsulation of Polysilicon Gate and Interconnect", Application Serial No: 08/995,875, Filing Date Dec. 22, 1997, Claims from corresponding U.S. Patent application (Atty Dkt: LS11P106).
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Castagnetti Ruggero
Giust Gary K.
Liu Yauh-Ching
Ramesh Subramanian
Fahmy Wael
LSI Logic Corporation
Pham Long
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