Metal bump with an insulating sidewall and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C438S613000, C174S261000, C257S734000

Reexamination Certificate

active

06958539

ABSTRACT:
Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

REFERENCES:
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patent: 5783465 (1998-07-01), Canning et al.
patent: 5844314 (1998-12-01), Kim
patent: 5923080 (1999-07-01), Chun
patent: 6111628 (2000-08-01), Shiota et al.
patent: 6228689 (2001-05-01), Liu
patent: 6232563 (2001-05-01), Kim et al.
patent: 64-44049 (1989-02-01), None
patent: 02-220863 (1990-09-01), None
patent: 4-196434 (1992-07-01), None
patent: 06-008599 (1994-01-01), None
patent: 6-232211 (1994-08-01), None
patent: 08-072486 (1996-03-01), None
patent: 00171099 (1998-10-01), None
patent: 00225398 (1999-07-01), None

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