Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-06-16
2001-11-27
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S220000, C365S230030
Reexamination Certificate
active
06324116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor memory device which includes a cache memory. A DRAM having a large storage capacity is used as a main memory, and an SRAM having a smaller storage capacity is used as the cache memory and both are provided on a semiconductor chip. The present invention also relates to a data transferring method for the semiconductor device.
2. Description of the Related Art
Generally, a data processing system uses a typical DRAM having a large storage capacity to reduce the cost of the system. However, recently, the operating speed of microprocessing units (MPU) has increased to 250 Mhz or greater. Although the operating speed of DRAMs has significantly increased, their operating speed is much less than the operating speed of today's MPU. Research has been performed in different areas attempting to solve the reduction in operating speed of a data processing system due to the difference in operating speed between the associated DRAM and an MPU. One solution is to use a merged memory with logic (MML) in which a DRAM together with a logic circuit are provided on a chip. A further proposed solution involves installing a DRAM, an SRAM which is a cache memory, and a logic circuit on a single chip. In this latter proposed solution, in which a DRAM, an SRAM and a logic circuit are installed on a chip, a circuit is required for effectively transferring data between the SRAM and the DRAM. However, up to now, no method for effectively transferring data between an SRAM and a DRAM has been developed.
SUMMARY OF THE INVENTION
In accordance with the present inventions, a semiconductor device is provided which effectively transmits data between a DRAM and an SRAM which are included on a same chip.
In accordance with another aspect of the present invention, a method is provided for effectively transmitting data between a DRAM and an SRAM.
According to one embodiment of the present invention, a semiconductor device is provided which includes a first memory cell array having a plurality of memory cells, and a second separate memory cell array having a plurality of memory cells, the semiconductor device including first circuitry responsive to a first control signal to simultaneously perform a reading operation of the first memory cell array and a writing operation of the second memory cell array, and the semiconductor device includes second circuitry responsive to a second control signal to simultaneously perform a writing operation of the first memory cell array and a reading operation of the second memory cell array.
According to another aspect of the present invention in the immediately preceding embodiment, the first memory cell array is comprised of a dynamic random access memory (DRAM), and the second memory cell array is comprised of a static random access memory (SRAM).
In another embodiment of the present invention, a semiconductor device is provided which includes a DRAM having a plurality of first memory cells which are arranged in rows and columns, a pair of input and output lines for transferring data in a selected one of the first memory cells, an input and output sense amplifier coupled to the pair of input and output lines for amplifying data on pair of input and output lines in a first mode, and a write driver for driving received data to the pair of input and output lines in a second mode; and an SRAM comprising a plurality of second memory cells which are arranged in rows and columns, a write bit line for transferring data output from the DRAM in the first mode, a write word line for controlling the data on the write bit line to be transmitted to a selected one of the second memory cells in the first mode, a read word line for controlling data to be read from the selected second memory cell in the second mode, and a read bit line for transmitting the data read from the second memory cell to the DRAM. In this embodiment, wherein the reading operation of the DRAM and the writing operation of the SRAM are simultaneously controlled by a first control signal in the first mode, and the reading operation of the SRAM and the writing operation of the DRAM are simultaneously controlled by a second control signal.
In a further embodiment of the present invention, a method is provided for transferring data in a semiconductor device which includes a DRAM and an SRAM. In the method, the semiconductor device includes a DRAM having a plurality of first memory cells which are arranged in rows and columns, a pair of input and output lines for transferring data in a selected one of the first memory cells, and an input and output sense amplifier coupled to the pair of input and output lines for amplifying data on the pair of input and output lines in a first mode; and an SRAM comprising a plurality of second memory cells which are arranged in rows and columns, a write bit line for transferring data which is output from the DRAM, in the first mode, and a write word line for controlling the data on the write bit line to be transferred to a selected one of the second memory cells in the first mode. The method comprises: (a) generating an internal clock signal in a synchronization with an external clock signal; (b) precharging the input and output lines to the same voltage level, in synchronization with the internal clock signal; (c) transferring the data on a selected first memory cell to the precharged input and output lines; (d) sensing and amplifying the data transferred from the first memory cell by enabling the input and output sense amplifier; (e) outputting the amplified data from the DRAM; (f) providing a logic unit operative in response to receipt of the internal clock signal and latency information to produce an output signal; (g) generating a DRAM read control signal by delaying an output signal from said logic unit for a predetermined delay time with respect to the internal clock signal when a CAS latency is less than or equal to a predetermined length; and (h) writing data in the second memory cells in response to the DRAM read control signal and activation of the write word line of the SRAM in the second mode.
According to another embodiment, a further method is provided for transferring data in an semiconductor device which includes a DRAM and an SRAM. In this embodiment, the semiconductor device includes a DRAM having a plurality of first memory cells which are arranged in rows and columns, a pair of input and output lines, and a write driver for driving received data to the pair of input and output lines in a second mode; and an SRAM having a plurality of second memory cells which are arranged in rows and columns, a read word line for controlling data to be read from a selected second memory cell in the second mode, and a read bit line for transferring data which is read from the selected second memory cell to the DRAM. The method comprises: (a) generating an internal clock signal in a synchronization with an external clock signal; (b) generating in synchronization with the internal clock signal a DRAM write control signal for controlling the read word line of the SRAM; (c) activating the read word line of the SRAM in response to the DRAM write control signal; (d) outputting data from the SRAM; (e) generating a predetermined write signal in synchronization with the internal clock signal; and (f) storing data which is output from the SRAM in a selected one of the first memory cells via the pair of input and output lines in response to the write signal.
REFERENCES:
patent: 6072741 (2000-06-01), Taylor
patent: 6088760 (2000-07-01), Walker et al.
patent: 10-326486 (1998-12-01), None
patent: 10-326491 (1998-12-01), None
Patent Abstract of Japan JP10326491 Supplied from theesp@cenetDatabase.
Patent Abstract of Japan JP 10326486 Supplied from theesp@cenetDatabase.
Lee Jeong-seok
Noh Mi-jung
Heid David W.
Nguyen Hien
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
Zarabian Amir
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