Memory with synchronous bank architecture

Details Memory with synchronous bank architecture Memory with synchronous bank architecture

2006-10-03

2006-10-03

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S104000

Reexamination Certificate

active

07117291

ABSTRACT:
In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.

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N. Omori et al., “Compact central arbiters for memories with multiple read/write ports”, Electronics Letters, Jun. 21st, 2001, vol. 37, No. 13, pp. 811-813 (w/ English Translation).
H.J. Mattausch, “Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity”, IEICE Trans. Electron., vol. E84-C, No. 3, Mar. 2001, pp. 410-418.

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