Memory with combined line and word access

Details Memory with combined line and word access Memory with combined line and word access

2005-02-03

2009-11-10

Tsai, Henry W.H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S036000

Reexamination Certificate

active

07617338

ABSTRACT:
A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

REFERENCES:
patent: 4912632 (1990-03-01), Gach et al.
patent: 4918587 (1990-04-01), Pechter et al.
patent: 4929246 (1990-05-01), Sinofsky
patent: 5446845 (1995-08-01), Arroyo et al.
patent: 5669013 (1997-09-01), Watanabe et al.
patent: 5761478 (1998-06-01), Chen et al.
patent: 6341318 (2002-01-01), Dakhil
patent: 6351784 (2002-02-01), Neal et al.
patent: 6775727 (2004-08-01), Moyer
patent: 2002/0078268 (2002-06-01), Lasserre
patent: 2002/0087845 (2002-07-01), Dowling
patent: 2003/0229734 (2003-12-01), Chang et al.
patent: 2004/0260881 (2004-12-01), Chauvel et al.
Ackland, et al., A Single-Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP, Mar. 3, 2000, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, pp. 412-424.
Pahl, et al., Maximizing Data Transfer Efficiency with C5000 DMA Controller, Sep. 12, 2001, Texas Instrument, pp. 1- 58.
Horel, et al., UltraSPARC-III: Designing Third-Generation 64-Bit Performance, May-Jun. 1999, IEEE Micro, pp. 73-85.
Dominic Herity, Network Processor Programming, Jul. 31, 2001, Embedded Systems Design.

Affiliated with

Also associated with

Rating

Memory with combined line and word access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory with combined line and word access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with combined line and word access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4124576