Memory with 6T small aspect ratio cells having metal...

Details Memory with 6T small aspect ratio cells having metal... Memory with 6T small aspect ratio cells having metal...

2006-08-08

2006-08-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S369000

Reexamination Certificate

active

07087493

ABSTRACT:
A method of forming a memory circuit comprising six transistor memory cells. The memory cells comprise first and second inverters. The inverters comprise respective first and second drive transistors and first and second pull-up transistors. The method also forms a plurality of conducting plugs. A first conducting plug is coupled to the first inverter and a second conducting plug is coupled to the first pull-up transistor and to the gates of the second drive transistor and the second pull-up transistor. A third conducting plug is coupled to the second inverter and a fourth conducting plug coupled to the second pull-up transistor and to the gates of the first drive transistor and the first pull-up transistor. The method also forms conducting elements. A first conducting element contacts the first conducting plug and the second conducting plug and a second conducting element contacts the third conducting plug and the fourth conducting plug.

REFERENCES:
patent: 5656861 (1997-08-01), Godinho et al.
patent: 5691559 (1997-11-01), Kimura
patent: 5886375 (1999-03-01), Sun
“Highly Scalable and Fully Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect,” 0-7803-4700-6/98 IEEE; by M. Inohara, H. Oyamastu, Y Unno, Y FuKaura, S. Goto, Y. Egi, and M. Kinugawa.
“A Novel 6.4μm2Full-CMOS SRAM Cell with Aspect Ration of 0.63 in a High-Performance 0.25 μm-Generation CMOS Technology”; 0-7803-4700-6/98; 1998 IEEE; by K. J. Kim, J. M. Younn, S. B. Kim, J. H. Kim, S. H. Hwang, K. T. Kim, and Y. S. Shin.

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