Memory using packet controller and memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Details

C711S156000, C370S378000, C370S389000, C365S189070, C365S222000, C324S765010, C257S787000

Reexamination Certificate

active

07657713

ABSTRACT:
A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

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Schilling, Donald L. & Belove, Charles; Registers, Counters, and Arithmetic Circuits; Electronic Circuits: Discrete and Integrated, Second Edition, Copyright 1979; pp. v-vi and 648-650; McGraw-Hill Book Company; United States of America.
Taub, Herbert & Schilling, Donald; Registers and Counters; Digital Integrated Electronics; Copyright 1977; pp. v-vi and 325-326; McGraw-Hill Book Company; United States of America.

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