Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2004-09-24
2010-02-02
Thai, Tuan V (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S156000, C370S378000, C370S389000, C365S189070, C365S222000, C324S765010, C257S787000
Reexamination Certificate
active
07657713
ABSTRACT:
A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.
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Jang Hyun-Soon
Jeong Woo-Seop
Park Bok-Gue
Seo Dong-Il
Choe Yong
Samsung Electronics Co,. Ltd.
Thai Tuan V
Volentine & Whitt P.L.L.C.
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