Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-01-31
2006-01-31
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S185330
Reexamination Certificate
active
06993690
ABSTRACT:
A processing unit12that is provided in a memory unit10can transfer information that is stored in a corresponding address to a spare memory area and prohibit writing of information into the corresponding address when the number write operations to the respective addresses of flash memories11-1through11-3reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency. When the remaining capacity of a spare memory area reaches a set capacity, an indication lamp14may lit or a memory status signal may be transmitted to a processing unit21of a computer20and displayed on a display unit30. The memory processing unit12may lit the indication lamp14when the number write operations to the respective addresses of flash memories11-1through11-3reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency.
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Flash Memory Guide Book 1996, Fujitsu, pp. 2-9.
Hagiwara Sys-Com Co., Ltd.
Lamarre Guy J.
Patterson Thuente Skaar & Christensen P.A.
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