Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-29
2004-04-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C365S201000, C365S230010
Reexamination Certificate
active
06721915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing method for detecting a bit error of a memory (RAM, ROM).
2. Description of the Related Arts
In a conventional memory testing method, in order to detect an error, for example, read/write tests, etc. on the entire area of the memory are effected. However, in recent years, in such the conventional memory testing method, an undetactable error occurs. A contrivance for noises countermeasure or performance enhancement is incorporated into the memory as hardware, and then a configuration of the memory is complicated, so that the error peculiar to various memories occurs. For the reason, if a memory testing program is not executed making conscious the configuration of the interior of the memory, it is impossible to detect the error peculiar to the memory. For this reason, when the memory testing program is executed, detailed information in the internal configuration of the memory (address allocation) is necessitated.
However, the internal configuration of the memory differs in each manufacturer, and further in the most case, even the memory of the same type of the same manufacturer is different in the internal configuration according to the number of versions. For this reason, when the memory testing program is prepared so as to adapt for a certain memory, the internal configuration differs for the other memories. Therefore, the testing program could not be used, and it was necessary that the testing program is prepared from the beginning for the other memories.
In this manner, the conventional memory testing program was inefficient as it was necessary that the internal configuration is prepared in each same memory. Namely, as it was necessary that another testing program is prepared from the beginning with respect to the memory having a different internal configuration, there was a problem that the number of processes of developing a testing program is enormous.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory testing method according to a versatile testing program not depending upon an internal configuration of a memory.
In order to achieve the above object, according to a first aspect of the present invention there is provided a memory testing method for detecting an error of a memory by executing a testing program accessing the memory, comprising the steps of:
inputting correspondence information between each of a plurality of physical addresses in the memory and a program address designated by the testing program for accessing the respective physical addresses, from externally to the testing program; and
designating the program address so as to access at least the one physical address of the memory in accordance with the correspondence information.
According to this memory testing method, it becomes possible to use versatilely the testing program with respect to a plurality of memories which are different respectively in correspondence information.
In order to achieve the above object, according to a second aspect of the present invention there is provided a memory testing method for detecting an error of a memory by executing a testing program accessing the memory to write data therein, comprising the steps of:
inputting correspondence information between first data of at least 1 bit to be written into the memory and second data of at least 1 bit to be designated by the testing program for writing the first data into the memory, from externally to the testing program; and
designating the second data so as to write the first data into the memory in accordance with the correspondence information.
Thus, in the case where data specified by the testing program are different from data written into the memory in each memory, it is possible to use versatilely the testing program with respect to the plurality of memories.
In order to achieve the above object, according to a third aspect of the present invention there is provided a memory testing method for detecting an error of a memory by executing a testing program accessing the memory, comprising the steps of:
measuring an access speed to the memory or a value corresponding thereto by a plurality of program addresses which are designated by the testing program for accessing the physical addresses of the memory and have a plurality of bit values different from each other; and
acquiring a data format of the program address based on the access speed or the value corresponding thereto.
Thus, in the case where a data format of a program address for designating a physical address of the memory is unclear, it becomes possible to presume the data format. the data format of the program address includes a bit corresponding to each identifier of a row address and column address constituting the physical address of the memory, a bank, each memory of a plurality of memories and each memory controller for controlling the plurality of memories of a plurality of memory controllers.
In order to achieve the above object, according to a fourth aspect of the present invention there is provided a memory testing method for detecting an error of a memory by executing a testing program accessing the memory, comprising the steps of:
selecting arbitrary one of all combinations of correspondence information between each of the plurality of physical addresses in the memory and a program address designated by the testing program for accessing each of the physical addresses;
continuously accessing the plurality of physical addresses based on the selected combination of correspondence information; and
in the case where a first error is detected in the step of accessing, abstracting at least one combination in which the plurality of physical addresses detected the first error are adjacent to each other from the all combinations of the correspondence information.
Thus, it becomes possible to presume correspondence information between the physical address of the memory and a program address specified by the testing program.
In the case of a plurality of the abstracted combinations of the correspondence information, arbitrary combination is further selected from the abstracted combinations of the correspondence information, and the plurality of physical addresses are continuously accessed based on the selected combination of correspondence information. In the case where a second error is detected, it is further abstracted at least one combination in which the plurality of physical addresses detected the second error are adjacent to each other from the abstracted combinations of the correspondence information.
By repeating this process, the correspondence information can be specified.
REFERENCES:
patent: 5457658 (1995-10-01), Niijima et al.
patent: 5477494 (1995-12-01), Miyagawa et al.
patent: 5699509 (1997-12-01), Gary et al.
patent: 5758056 (1998-05-01), Barr
patent: 6108745 (2000-08-01), Gupta et al.
patent: 6134677 (2000-10-01), Lindsay
patent: 6202180 (2001-03-01), Nose
patent: 0 977 121 (2000-02-01), None
patent: A-60-246100 (1985-12-01), None
patent: A-5-159598 (1993-06-01), None
patent: A-7-191099 (1995-07-01), None
Furukawa Takeshi
Matsumoto Akiko
Sato Satoshi
Arent & Fox PLLC
De'cady Albert
Fujitsu Limited
Gandhi Dipakkumar
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