Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-09-21
2002-11-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000
Reexamination Certificate
active
06477672
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing a non-volatile memory from which the stored data call be electrically erased ill all bits en bloc or in block by block en bloc and in which data can be rewritten, the non-volatile memory being called, for example, a flash memory, a flash EEPROM or flash E
2
PROM (flash electrically erasable programmable read only memory), or the like.
2. Description of the Related Art
Among PROMs (programmable read only memories) which are rewritable read only memories is called “flash memory” in this technical field a memory the stored contents of which is replaceable by electrically erasing the stored contents in all bits en bloc or in block by block en bloc and rewriting data therein. As shown in
FIG. 8
, the inside of this flash memory (for example, NAND type flash memory) is separated into a plurality of blocks (in this example, 1024 blocks of No. 1 to No. 1024). Each of the blocks is constituted by N pages (N is an integer equal to or greater than 2), and each of the N pages is constituted by M bits (M is an integer equal to or greater than 2). Such flash memory is constructed such that the stored contents thereof can be electrically erased not only in all bits en bloc but also in block by block en bloc, and the stored contents thereof can be replaced by rewriting data in one block or in all blocks the stored contents of each of which have. been erased. In general, there are many cases that each block comprises 16 pages (N=16) and each page comprises 512 bits (M=512).
Conventionally, this flash memory is tested and measured by a memory testing apparatus for testing and measuring a commonplace memory (for example, a memory constituted by a semiconductor integrated circuit (IC)).
FIG. 9
shows a configuration of a ordinary memory testing apparatus that has conventionally been used.
The illustrated memory testing apparatus comprises a main controller
100
, a testing apparatus proper
200
.called “main frame” in this technical field and a test head
300
. The testing apparatus proper
200
comprises, in this example, a timing generator TG, a pattern generator PG, a waveform formatter FC, drivers DR, a voltage comparator VCP, a logical comparator LOC and a failure analysis memory AFM.
The test head
300
is constructed separately from the testing apparatus proper
200
, and a predetermined number of device sockets (not shown) are usually mounted on the top portion of the test head
300
. In addition, a printed board called “pin card” in this technical field is accommodated within the test head
300
, and a circuit containing the drivers DR and the voltage comparator VCP of the testing apparatus proper
200
is usually formed on this pin card. In general, the test head
300
is mounted to a test section of a semiconductor device transporting and handling apparatus called “handler” in this technical field, and the test head
300
is electrically connected to the testing apparatus proper
200
by signal transmission means such as cables, optical fibers or the like.
A memory to be tested (a memory under test) MUT is mounted on a device socket of the test head
300
, through which a test pattern signal is written in the memory under test MUT from the testing apparatus proper
200
and a response signal read out of the memory under test MUT is supplied to the testing apparatus proper
200
, thereby to perform the test and the measurement for the memory under test MUT.
Further, in
FIG. 9
only the drivers DR are shown in the plural form (four in this example), but, in reality, there are provided a predetermined number of drivers DR, for example 512 drivers. In addition, in
FIG. 9
, in order to simplify the drawing, each of the components in the main frame
200
(the timing generator TG, the pattern generator PG, the waveform formatter FC, the voltage comparator VCP, the logical comparator LOC and the failure analysis memory AFM) except the drivers DR is shown as one block, but in practice the remaining components in the main frame
200
except the timing generator TG are also provided by the same number (512) as that of the drivers DR, respectively. That is, only the timing generator TG is used in common to each of the pins of the IC under test MUT.
The main controller
100
is constituted by a computer system having its scale of, for example, a workstation or so, and a test program
101
created by a user (programmer) is previously stored therein, and the entire memory testing apparatus is controlled in accordance with the test program
101
. The main controller
100
is connected to the timing generator TG, the pattern generator PG, and the like in the main frame
200
via a tester bus
201
. A test for the memory under test MUT is carried out in accordance with control instructions/commands outputted from the main controller
100
.
A pattern generating sequence described in the test program stored in the main controller
100
is previously stored in the pattern generator TG prior to the start of a test. When a test start instruction is given thereto from the main controller
100
, the pattern generator PG outputs test pattern data to be applied to the memory under test MUT in accordance with the stored pattern generating sequence. As the pattern generator PG, an ALPG (Algorithmic Pattern Generator) is generally used. The ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by an arithmetic and logic operation or computation using internal registers each having an arithmetic and logic function or computing function.
The timing generator TG has timing data previously stored therein prior to the start of a test, the timing data being described in the test program stored in the main controller
100
and outputted for every test period. The timing generator TG outputs a clock pulse (a timing pulse) for each test period in accordance with the stored timing data. This timing pulse is supplied to the waveform formatter FC, the logical comparator LOC and the like.
The waveform formatter FC defines a rise timing and a fall timing of a logical waveform, based on the test pattern data outputted from the pattern generator PG and the timing pulse outputted from the timing generator TG, to produce a test pattern signal having a real waveform that changes from/to logical H (logical “1”) to/from logical L (logical “0”). This test pattern signal is applied to the memory under test MUT via the drivers DR.
Each of the drivers DR defines the amplitude of the test pattern signal outputted from the waveform formatter FC to a desired amplitude (logical H, i.e., voltage of logical “1” and logical L, i.e., voltage of logical “0”) and applies such test pattern signal to the device socket of the test head
300
, thereby to drive the memory under test MUT.
The voltage comparator VCP determines whether or not a logical value of a response signal outputted from the memory under test MUT has a normal voltage value. That is, the voltage comparator VCP determines whether or not a voltage of logical H has a value equal to or greater than a defined voltage value in case of the response signal of logical H and whether or not a voltage of logical L has a value equal to or less than a defined voltage value in case of the response signal of logical L.
In case the determination result of the voltage comparator VCP indicates a good result (pass), the output signal of the voltage comparator VCP is inputted to the logical comparator LOC where it is compared with an expected value pattern data (signal) EXP supplied from the pattern generator PG to determine whether or not the memory under test MUT has outputted a normal response signal. The comparison result of the logical comparator LOC is stored in the failure analysis memory AFM.
When the output signal of the voltage comparator VCP is not in accord with the expected value pattern data, the logical comparator LOC determines a memory cell of the memory under test MUT at the address
Advantest Corporation
De'cady Albert
Gallagher & Lathrop
Lamarre Guy
Lathrop, Esq. David N.
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