Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-04-14
2001-09-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000
Reexamination Certificate
active
06295620
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a test facilitation circuit built into a memory device such as a dynamic random-access memory.
A dynamic random-access memory (DRAM) is tested by writing various test data patterns into its memory-cell array, then reading the written data. A test facilitation circuit speeds up the testing process by providing a high-speed synchronous interface between the memory device and external test equipment, and an auxiliary memory circuit for temporary storage of the test data within the memory device. The auxiliary memory circuit has a capacity equal to, for example, one row of memory cells in the memory-cell array.
In a conventional test facilitation circuit, test data are transferred into the auxiliary memory circuit until the auxiliary memory circuit is full, then written all at once into the memory-cell array. To write a test pattern into the memory-cell array, this two-step process is repeated for every row of memory cells, for example, so despite the high-speed synchronous interface, much time is consumed in the transfer of data from the test equipment to the auxiliary memory circuit. Further details will be given below.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to speed up the testing of memory devices.
The invented test facilitation circuit is integrated into a memory device having a main memory circuit with a plurality of memory cells. The test facilitation circuit comprises an auxiliary memory circuit storing test data, an internal data bus coupling the auxiliary memory circuit to the main memory circuit, an interface circuit communicating with external test equipment, an auxiliary memory controller controlling the auxiliary memory circuit, and a main memory controller.
The main memory controller receives a test mode signal from the external test equipment. When the test mode signal is in one state, the main memory controller responds to a write request signal from the external test equipment by directing the auxiliary memory controller to transfer test data from the interface circuit to the auxiliary memory circuit, then by transferring the test data from the auxiliary memory circuit to the main memory circuit. When the test mode signal is in another state, the main memory controller responds to the write request signal by transferring test data immediately from the auxiliary memory circuit to the main memory circuit.
The invented method of testing a memory circuit comprises the steps of transferring test data from the external test equipment to the auxiliary memory circuit, storing the test data in the auxiliary memory circuit, and repeatedly transferring the test data from the auxiliary memory circuit to different locations in the main memory circuit.
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De'cady Albert
Gluck Jeffrey W.
OKI Electric Industry Co., Ltd.
Sartori Michael A.
Torres Joseph D.
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