Memory test device and method capable of achieving fast...

Details Memory test device and method capable of achieving fast... Memory test device and method capable of achieving fast...

1998-12-24

2001-11-27

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S719000, C365S201000

Reexamination Certificate

active

06324666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory test device and memory test method for deciding the presence or absence of a defective bit of a memory.
2. Description of Related Art
FIG. 6
is a block diagram showing a conventional memory test device. In
FIG. 6
, the reference numeral
1
designates a chip that mounts a memory
19
to be tested;
2
designates a tester for testing a memory
19
embedded in the chip
1
;
3
designates a pattern program storing memory
3
for storing a test pattern and the like; and
4
designates a pattern generator that when writing the test pattern in the memory
19
, supplies control level generators
5
with a write request of the test pattern, and supplies address level generators
6
with write addresses of the test pattern, and when reading the test pattern, supplies the control level generators
5
with a read request of the test pattern, and supplies the address level generators
6
with the read addresses of the test pattern. The pattern generator
4
acquires, when producing the write request or read request of the test pattern, a data pattern from the pattern program storing memory
3
, and supplies data level generating comparators
7
with the test pattern in accordance with the data pattern.
Each reference numeral
5
designates the control level generator that receives from the pattern generator
4
the write request or read request of the test pattern, and supplies it to one of control test pins
9
; each reference numeral
6
designates the address level generator that receives from the pattern generator
4
the write address or read address of the test pattern, and supplies it to one of address test pins
10
; and each reference numeral
7
designates the data level generating comparator that supplies, when receiving from the pattern generator
4
the test pattern to be written in the memory
19
, one of the data test pins
11
with an H or L level signal corresponding to the test pattern (the H or L level signal corresponding to the test pattern will be called a “test pattern signal” from now on), and supplies, when receiving from the pattern generator
4
the test pattern which is expected to match the test pattern to be read from the memory
19
, generates an expected value (H or L level value) corresponding to the test pattern, and compares the expected value with the signal level supplied from one of the data test pins
11
.
The reference numeral
8
designate a total decision maker for deciding the presence or absence of a defective bit in the memory
19
in response to compared results supplied from individual data level generating comparators
7
;
9
designates the control test pins connected to control pins
12
of the chip
1
;
10
designates the address test pins connected to address pins
13
of the chip
1
;
11
designates the data test pins of the tester
2
, which are connected to data pins
14
of the chip
1
;
12
designates the control pins of the chip
1
, which are connected to the control test pins
9
of the tester
2
;
13
designates the address pins of the chip
1
, which are connected to the address test pins
10
of the tester
2
, and
14
designates the data pins of the chip
1
, which are connected to the data test pins
11
of the tester
2
.
The reference numeral
15
designates a CPU of the chip
1
;
16
designates a bus controller that supplies, when receiving from the tester
2
the write request or read request of the test pattern through the control test pins
9
and control pins
12
, a memory
19
with the write request or read request, and that instructs an address controller
17
to supply the memory
19
with the write address or read address of the test pattern, and instructs a data bus controller
18
on the transfer direction of the test pattern;
17
designates the address controller that receives the write address or read address of the test pattern from the address pins
13
under the instructions of the bus controller
16
, and supplies the memory
19
with the write address or read address;
18
designates the data bus controller for controlling the transfer direction of the test pattern under the instructions of the bus controller
16
; and
19
designates the memory that when receiving from the bus controller
16
the write request of the test pattern, receives the test pattern signals from the data pins
14
through the data bus controller
18
and a data input/output bus
18
b
, and writes the test pattern signals to the write address fed from the address controller
17
, and that when receiving from the bus controller
16
the read request of the test pattern, reads the test pattern signals stored in the read address fed from the address controller
17
, and supplies the read test pattern signals to the data pins
14
. Finally, the reference numeral
20
designates a test result pin.
Next, the operation of the conventional memory test device will be described.
First, the write process of the test pattern into the memory
19
will be described for making a decision as to whether a defective bit is present or not in the memory
19
.
In this case, it is necessary for the pattern generator
4
to have the chip
1
recognize that the test pattern is to be written into the memory
19
from now on. Thus, the pattern generator
4
supplies the control level generators
5
with the write request of the test pattern, and the address level generators
6
with the write address of the test pattern.
In response to this, the control level generators
5
supply the bus controller
16
of the chip
1
with the write request of the test pattern through the control test pins
9
and control pins
12
, and the address level generators
6
supply the address controller
17
of the chip
1
with the write address of the test pattern through the address test pins
10
and address pins
13
. In the course of this, to supply the chip
1
with the test pattern to be written into the memory
19
, the pattern generator
4
acquires the data pattern from the pattern program storing memory
3
, and supplies the data level generating comparators
7
with the test pattern in accordance with the data pattern.
Receiving the test pattern from the pattern generator
4
, the data level generating comparators
7
supply the data test pins
11
with the H or L level signals (test pattern signals) corresponding to the test pattern.
In this case, the data level generating comparators
7
are connected with the data test pins
11
in a one-to-one correspondence, and hence when the number of the data test pins
11
is
16
, there are
16
data level generating comparators
7
. Thus, the number of bits of the data is limited to
16
that can be transferred from the tester
2
to the chip
1
at a time. Accordingly, to write a 128-bit test pattern, for example, it must be divided into eight parts (128 bits/16 bits=8).
When the tester
2
supplies the chip
1
with the write request and write address of the test pattern, and the test pattern signals, the bus controller
16
supplies the memory
19
with the write request of the test pattern, and the address controller
17
provides the memory
19
with the write address of the test pattern.
In response to this, the memory
19
repetitively captures from the data pins
14
the test pattern signals eight times, and writes the test pattern signals into the write addresses.
After completing the write process of the test pattern into the memory
19
, the test pattern is read from the memory
19
to decide whether the test pattern agrees with its expected values.
First, it is necessary for the pattern generator
4
to have the chip
1
recognize that the test pattern is to be read from the memory
19
from now on. Thus, the pattern generator
4
supplies the control level generators
5
with the read request of the test pattern, and the address level generators
6
with the read address of the test pattern.
In response to this, the control level generators
5
supply the bus controller
16
of the chip
1
wit

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