Memory system with write protection

Details Memory system with write protection Memory system with write protection

1983-01-03

1987-05-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 700

Patent

active

046655069

ABSTRACT:
A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source. The control circuit in the memory system is provided with an override capability to override the write protection circuits.

REFERENCES:
patent: 4398269 (1983-08-01), Hedin et al.
patent: 4453236 (1984-06-01), Uratani et al.

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