Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-06-09
2008-11-25
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000
Reexamination Certificate
active
07456650
ABSTRACT:
Provided is a memory system in which a pair of differential signals transmitted via a pair of transmission lines are prevented from being terminated at the same voltage during a standby mode, thereby preventing a receiver from entering an unstable state. The memory system includes a pair of transmission lines, a transmitter that outputs a pair of differential signals to the pair of transmission lines, and a receiver that receives the pair of differential signals via the pair of transmission lines. A first termination voltage is applied to one of the pair of transmission lines, and a second termination voltage is applied to the other transmission line. The first termination voltage is determined to be different from the second termination voltage.
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Cho James H.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
White Dylan
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