Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-11-28
1997-03-25
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Testing
365210, 371 211, G11C 700
Patent
active
056151594
ABSTRACT:
A memory system (preferably implemented as an integrated circuit) including an array of memory cells, a control unit for controlling operations of the system (such as programming, reading, and erasing the cells), at least one data storage unit which stores control parameter data determining at least one control parameter for the system, and default parameter circuitry for asserting at desired times one or both of: default control parameter data (regardless of the control parameter data stored in each data storage unit); and at least one default voltage level (in place of an otherwise asserted voltage level). In preferred embodiments, the default control parameter data (or voltage levels) are asserted during a test initialize mode in response to an initialization signal generated by the control unit, for use in initializing internal control registers (and voltage levels) of the system so that an external program for controlling the system during the test mode can start from a known condition. Other embodiments are methods for asserting default control parameter data of memory systems at desired times during system operation (regardless of the values of control parameter data stored in storage units of the system), methods for asserting default voltage values at desired times during operation of such systems, and memory systems capable of performing such methods.
REFERENCES:
patent: 5031142 (1991-07-01), Castro
patent: 5047664 (1991-09-01), Moyal
patent: 5371712 (1994-12-01), Oguchi et al.
patent: 5457696 (1995-10-01), Mori
patent: 5467314 (1995-11-01), Miyazawa et al.
Dinh Son T.
Micron Quantum Devices Inc.
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