Memory system with cyclic redundancy check

Details Memory system with cyclic redundancy check Memory system with cyclic redundancy check

2008-01-14

2011-10-18

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000

Reexamination Certificate

active

08042023

ABSTRACT:
A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum.

REFERENCES:
patent: 7076715 (2006-07-01), Gibart
patent: 7200770 (2007-04-01), Hartwell et al.
patent: 7203890 (2007-04-01), Normoyle
patent: 2001/0049789 (2001-12-01), Schmid
patent: 2009/0235113 (2009-09-01), Shaeffer et al.

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