Memory system with bit-line discharging mechanism

Details Memory system with bit-line discharging mechanism Memory system with bit-line discharging mechanism

2007-03-13

2007-03-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S204000, C365S205000, C365S189050

Reexamination Certificate

active

11128846

ABSTRACT:
A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.

REFERENCES:
patent: 7085184 (2006-08-01), Walther et al.
patent: 2006/0013041 (2006-01-01), Lin

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