Memory system that sets a predetermined phase relationship...

Details Memory system that sets a predetermined phase relationship... Memory system that sets a predetermined phase relationship...

2005-05-24

2005-05-24

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C365S233100, C713S500000

Reexamination Certificate

active

06898726

ABSTRACT:
A clock system for a data bus, e.g., a memory bus system, provides a write data (WCLK) clock signal in one direction on a bus and a data read (RCLK) clock signal in an opposite direction on the bus. A predetermined phase relationship between said WCLK and RCLK clock signals is set at a predetermined location on the data bus to ensure that all memory subsystems connected to the bus receive the WCLK and RCLK signals with appropriate timing to ensure proper operation of the memory subsystems.

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