Memory system having stub bus configuration

Details Memory system having stub bus configuration Memory system having stub bus configuration

2007-12-25

2007-12-25

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000

Reexamination Certificate

active

10043047

ABSTRACT:
A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

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