Memory system having data inversion and data inversion...

Details Memory system having data inversion and data inversion... Memory system having data inversion and data inversion...

2007-06-26

2007-06-26

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C365S202000, C365S189011, C710S100000

Reexamination Certificate

active

10737861

ABSTRACT:
A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

REFERENCES:
patent: 6826095 (2004-11-01), Macri et al.
patent: 2001/0052057 (2001-12-01), Lai et al.
patent: 2004/0065904 (2004-04-01), Yoshida et al.
patent: 2005/0182894 (2005-08-01), LaBerge
“ELPIDA 128M bits Self Terminated Interface DDR SDRAM” data sheets, Nov. 2002, pp. 1-46.

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