Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-01-10
2003-06-24
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S203000
Reexamination Certificate
active
06584028
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory system, and more particularly, to a memory system and a semiconductor memory device for enhancing bus efficiency and a refresh method of the semiconductor memory device.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices must periodically perform refresh operations. As the memory capacity of DRAM devices increases, the number of refresh operations to be performed for a given time also increases. Accordingly, a refresh command accounts for a larger percentage of DRAM control commands in a memory system using DRAMs, and thus bus efficiency continues to decrease.
For example, in the case of a 256 Mbit synchronous dynamic random access memory (SDRAM) operating at a frequency of 100 MHz with a tRFC of 70 ns and a refresh interval of 32 ms and having a page size of 1 Kbyte, the percentage of the time required to perform a refresh operation with respect to the whole operational time of the SDRAM can be obtained from Equation (1). Here, the tRFC represents a minimum time taken to activate and precharge a wordline during a refresh operation.
256
Mbit
1
Kbyte
×
70
ns
32
ms
=
7.168
%
(
1
)
In the case of a 4 Gbyte SDRAM operating at a frequency of 100 MHz with a tRFC of 70 ns and a refresh interval of 32 ms and having a page size of 4 Kbyte, the percentage of the time required to perform a refresh operation with respect to the whole operational time of the SDRAM can be obtained from Equation (2).
4
Gbit
4
Kbyte
×
70
ns
32
ms
×
100
=
28.672
%
(
2
)
Referring to Equations (1) and (2), as the memory capacity of semiconductor memory devices increases, the percentage of the time taken to perform a refresh operation with respect to the operational time of the SDRAM increases, and thus the efficiency of memory bus usage decreases.
In the case of recently developed rambus DRAM, during selective refresh of particular banks in the DRAM which is comprised of a plurality of banks so as to increase the efficiency of a memory bus, the other banks not to be refreshed can perform operations other than a refresh operation. In this case, it is still impossible to apply operations other than a refresh operation to the particular banks being refreshed during the refresh time period tRFC. In such a memory device which is capable of selectively performing refresh operations on particular banks and thus increasing bus efficiency, supposing that tRRD=17.5 ns and activation commands are consecutively applied to the memory device, the percentage of the time period by which the refresh command operations occupy the memory bus can be obtained from Equation (3), which represents the case of the 256 Mbit SDRAM, and Equation (4), which represents the case of the 4 Gbit SDRAM.
256
Mbit
SDRAM
:
256
Mbit
1
KByte
×
17.5
ns
32
ms
×
100
=
1.792
%
(
3
)
4
Gbit
SDRAM
:
4
Gbit
4
KByte
×
17.5
ns
32
ms
×
100
=
7.168
%
(
4
)
Comparing Equations (1) and (3), in the case of selectively refreshing particular banks, the percentage of the memory bus occupied by a refresh command can be considerably decreased. However, with reference to Equation (4), memory devices having a large memory capacity, such as the 4 Gbit SDRAM, still have a problem with a high memory bus occupancy percentage by the refresh command.
In addition, in actually operating a memory device, particular banks, to which refresh commands are desirably applied, may be in an open state, and in that case, precharge commands must be applied to the open banks before applying the refresh commands to the open banks. Here, “the open banks” indicate that the wordline of each of the banks is enabled.
FIG. 1
is a diagram illustrating commands externally applied to refresh an open bank and the operation of a semiconductor memory device in accordance with such commands. For the convenience of explanation, it is supposed that a semiconductor memory device dealt with in
FIG. 1
periodically performs refresh operations and every command applied to the semiconductor memory device is generated in a memory controller.
Referring to
FIG. 1
, the memory controller initially applies a precharge command P
1
to the semiconductor memory device in order to refresh a bank i in an active state and then applies a refresh command R
1
to the semiconductor memory device. The semiconductor memory device performs a precharge operation P
2
on the bank i in response to the precharge command P
1
and performs a refresh operation on the bank i by activating A
4
a wordline of the bank i in response to the refresh command R
2
. After the wordline of the bank i is refreshed, the semiconductor memory device performs a precharge operation P
3
on the refreshed wordline of the bank i. At this time, a row address (the address of a wordline) required for a refresh operation is generated in itself in the semiconductor memory device. After the wordline of the bank i is refreshed, the memory controller applies an activation command A
2
to the semiconductor memory device in order to activate the bank i. The semiconductor device activates A
5
the wordline of the bank i in response to the activation command A
2
.
In other words, the memory controller must apply the precharge command P
1
, the refresh command R
1
, and the activation command A
2
to a semiconductor memory device in order to refresh an open bank and reopen the refreshed bank in the semiconductor memory device. Accordingly, the number of commands, which must be applied to the semiconductor memory device in order to refresh an open bank, increases, and thus the bus efficiency decreases.
SUMMARY OF THE INVENTION
To address the above-described limitations, it is a first object of the present invention to provide a refresh method of a semiconductor memory device, which is capable of increasing bus efficiency by performing a refresh operation on an open bank after precharging the bank without a precharge command being applied.
It is a second object of the present invention to provide a semiconductor memory device, which is capable of increasing bus efficiency by performing a refresh operation on an open bank in response to a refresh command.
It is a third object of the present invention to provide a memory system, which is capable of increasing bus efficiency by performing a refresh operation on memory devices following the above refresh method.
In one aspect, the present invention is directed to a method for refreshing an open bank of a semiconductor memory device under control of a memory controller in a memory system comprising a plurality of semiconductor memory devices and the memory controller for controlling the plurality of semiconductor memory devices. A refresh command is received from the memory controller in order to refresh the open bank. The open bank is recharged in response to the refresh command, and the precharged bank is refreshed.
The method may further comprise the step of activating the refreshed bank so as to restore the refreshed bank to its former condition.
In another aspect, the present invention is directed to a semiconductor memory device, which refreshes a bank in response to a refresh command generated by a memory controller. The semiconductor memory device comprises a refresh controller, which first precharges the bank and then refreshes the precharged bank in response to the refresh command, if the bank to be refreshed is an open bank.
The refresh controller may comprise a precharger precharging the corresponding bank in response to a precharge signal; an activator activating the corresponding bank in response to an
Hoang Huan
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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