Memory system and method using ECC to achieve low power refresh

Details Memory system and method using ECC to achieve low power refresh Memory system and method using ECC to achieve low power refresh

2005-11-15

2005-11-15

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S200000, C365S230040

Reexamination Certificate

active

06965537

ABSTRACT:
Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndromes are generated and stored. When transitioning from the reduced power refresh mode, data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data. The syndromes are also used to correct any errors that are found, and the corrected data are written to the rows of memory cells. By correcting any errors that exist when transitioning from the reduced power refresh mode, it is not necessary to use the syndromes to detect and correct errors while operating in the reduced power refresh mode.

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