Memory system, a memory device, a memory controller and...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S233130, C365S189050, C365S194000

Reexamination Certificate

active

07974143

ABSTRACT:
The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.

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patent: WO 97/08702 (1997-03-01), None
patent: WO 01/75616 (2001-10-01), None
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification; JESD79D (Revision of JESD79C), Jan. 2004, JEDEC Solid State Technology Association.

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