Memory system

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189080

Reexamination Certificate

active

06856554

ABSTRACT:
A memory system has a memory controller, a plurality of memory modules and a memory bus connected to the memory controller and branching into a plurality of sub-busses, each of which is connected to a memory module. A sub-bus has a diode associated therewith for isolating a memory module connected to that sub-bus from the memory bus.

REFERENCES:
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patent: 6028781 (2000-02-01), Vogley et al.
patent: 6333890 (2001-12-01), Niimi et al.
patent: 6338113 (2002-01-01), Kubo et al.
patent: 6349051 (2002-02-01), Klein
patent: 6393541 (2002-05-01), Fujii
patent: 6414891 (2002-07-01), Kuge et al.
patent: 20020083255 (2002-06-01), Greeff et al.
patent: 0001207 (2000-01-01), None
patent: 0075796 (2000-12-01), None

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