Memory subsystem including an error detection mechanism for...

Details Memory subsystem including an error detection mechanism for... Memory subsystem including an error detection mechanism for...

2005-09-06

2005-09-06

Beausoliel, Robert (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S768000, C714S805000

Reexamination Certificate

active

06941493

ABSTRACT:
A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.

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International search report application No. PCT/US03/03388 mailed Mar. 29, 2004.

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