Memory self-test via a ring bus in a data processing apparatus

Details Memory self-test via a ring bus in a data processing apparatus Memory self-test via a ring bus in a data processing apparatus

2007-11-06

2007-11-06

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C365S201000

Reexamination Certificate

active

11085599

ABSTRACT:
A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

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