Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-04-30
2001-06-05
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185090, C365S225700, C365S240000
Reexamination Certificate
active
06243305
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to redundancy circuitry for semiconductor memory devices, and particularly to row/column redundancy circuitry for random access memory (RAM) devices.
2. Background and Objects of the Invention
Processing defects in static random access memory (SRAM) and dynamic random access memory (DRAM) devices can significantly reduce the processing yield in large scale memory arrays. In order to improve the processing yield of memory chips, various methods of error correction have been created. These include ‘soft’ error correcting whereby software corrects for physical defects, and ‘hard’ error correcting whereby defective circuit elements are replaced with redundant elements included on the chip. The use of soft or hard error correcting can result in lower chip manufacturing costs and earlier introduction of new products on existing wafer fabrication lines or in new process technologies.
Yield enhancement by ‘hard’ error correcting on a memory chip is typically produced by including redundant rows and/or columns within the memory array. A few redundant rows or columns can significantly enhance yield of a memory circuit since many devices are rejected for single bit failure or failures in a single row or column. These redundant rows or columns can be added to the memory design to replace defective rows or columns which are identified at electrical test after wafer processing.
To replace a defective memory row or column, the defective row or column is first disconnected from the array. This is accomplished by one of three methods: current blown fuses, laser blown fuses, and laser annealed resistor connections. Then a redundant row or column is enabled and programmed with the defective row or column address.
Because any row or column of the memory array may be associated with a manufacturing defect, the above-described procedures for replacing a defective row or column line is conventionally carried out by providing a distinct fuse element for each row or column line. A problem exists, however, concerning the layout of the fuse elements and the memory array in that the fuse elements are large relative to the dimensions of a memory cell such that the pitch of a fuse element is generally greater than the column or row pitch for memory devices utilizing today's advanced fabrication techniques. Placing fuse elements on the column pitch has thus led to a number of compromises. One compromise, which includes replacing a number of row or column lines when only one row or column line needs to be replaced, requires the fabrication of more redundant row or column lines than would otherwise be needed. As a result, there exists a need for an improved method and circuit for replacing column or row lines in a memory device.
SUMMARY OF THE INVENTION
The present invention overcomes the shortcomings associated with prior redundancy architectures for memory devices and satisfies a significant need for a circuit and method for replacing defective row or column lines in a semiconductor memory device.
According to the present invention, there is provided a redundant circuit and method for a memory device having a plurality of row and column lines, including a programmable circuit for indicating at least one row or column line having a defect and a shifter circuit for shifting the memory addresses to bypass the at least one indicated defective row or column line. In particular, the shifter circuit modifies the address mapping for the row or column lines initially mapped to address values which are greater than the address value corresponding to the defective row or column line indicated by the programmable circuit. For each row or column line initially mapped to an address value which is greater than the address value corresponding to the defective row or column line, the shifter circuit maps a new address value to the row or column line which is one less than the address value initially mapped thereto. The highest numbered address values are mapped to a redundant row or column line. In this way, the defective row or column line is effectively bypassed.
A primary advantage of the present invention is that fuse elements in the programmable circuitry which may be utilized to indicate a defective row or column line are not coupled to the row or column line of the memory device. Instead, the programmable circuitry may be located in an area more peripherally located relative to the memory array.
In a first preferred embodiment of the present invention, the programmable circuitry is capable of indicating more than one defective row or column line in the memory device. Following the indication of at least two defective row or column lines in the memory device, for each row or column line initially mapped to an address value which is greater than a first address value corresponding to a first defective row or column line but less than a second address value corresponding to a second defective row or column line, the shifter circuit maps an address value to the row or column line which is one less than the address value initially mapped thereto. In addition, for each row or column line initially mapped to an address value which is greater than the second address value, the shifter circuit maps an address value to the row or column line which is two less than the address value initially mapped thereto. In this way, the address values which are greater than the first address value but less than the second address value are mapped to at least a next higher row or column line, and the address values which are greater than the second address value are twice shifted to higher row or column lines. The highest two address values are each mapped to a redundant row or column line. Consequently, both the first and second defective row or column lines are effectively bypassed.
In the first preferred embodiment of the present invention described above, the address value corresponding to a defective row or column line, generated by the programmable circuitry, is static so that an entire column or row line associated with at least one defect is permanently bypassed. In a second preferred embodiment of the present invention, the address value corresponding to a defective column line is dynamically generated in order to bypass the column line only when a previously discovered defective memory cell is to be accessed. In this way, a single redundant column line may be utilized to bypass defective memory cells associated with different column lines.
REFERENCES:
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patent: 5764587 (1998-06-01), Buettner et al.
patent: 5801986 (1998-09-01), Matsumoto et al.
patent: 5953267 (1999-09-01), Oh
patent: 5963489 (1999-10-01), Kirihata et al.
patent: 0 795 825 A2 (1997-09-01), None
patent: WO 98/28746 (1998-07-01), None
European Search Report dated Sept. 5, 2000 completed on Aug. 29, 2000, EP 00 30 3618.
Elms Richard
Galanthay Theodore E
Jorgenson Lisa K.
Nguyen Tuan T.
STMicroelectronics Inc.
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