Memory read circuitry

Details Memory read circuitry Memory read circuitry

2001-07-17

2003-01-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S194000, C365S189080

Reexamination Certificate

active

06512712

ABSTRACT:

1. FIELD OF THE INVENTION
The present invention generally relates to data processing systems. More specifically, the present invention relates to memory systems, precharge circuitry and read circuitry.
2. BACKGROUND
As technology advances, memories in semiconductor devices have become larger and more advanced. The number of memory cells on Dynamic Random Access Memories is ever increasing. In addition, modem microprocessors utilize register files that include a large number of registers. Such register files may include multiple read and write access ports. As a result, the register file can be quite large.
A semiconductor memory typically includes a memory cell array that has a grid of bitlines and wordlines, with memory cells located at intersections of the bitlines and the wordlines. During operation, the bitlines and the wordlines are selectively asserted and negated to enable at least one of the memory cells to be read or written.
Increasing demands for larger memories have driven increases in bitlines lengths and loading. The additional lengths of the bitlines and the device count per bitline add wire and diffusion capacitance to an already highly capacitive environment. As a result, additional time is required to charge and discharge this extra capacitance. Such additional time equates to increased read and write times and hence, slower performance.
To decrease the bitline capacitance, prior art memory systems split the bitline into global bitlines and local bitlines. One example of such a memory system is shown in U.S. Pat. No. 6,058,065 to Lattimore.
A prior art split bitline read circuit is shown in FIG.
1
. The read circuit includes a first local bitline, which would typically be coupled to a first group of memory cells (not shown). The read circuit also includes a second local bitline, which would typically be connected to a second group of memory cells (not shown). The local bitlines are connected to a local sense amp, which, as shown in
FIG. 1
, is a NAND gate
101
.
As is shown in
FIG. 1
, the first local bitline will be precharged through p-type metal oxide semiconductor (PMOS) transistor
102
when the precharge signal is low. Similarly, the second local bitline will be precharged through PMOS transistor
103
and the global bitline will be precharged high through PMOS transistor
104
when the precharge signal is low. Thus, grounding the precharge signal precharges the first bitline, the second bitline, and the global bitline.
When a memory cell is desired to be read, a local bitline, such as the first local bitline, will be conditionally discharged based upon the content of the memory cell, i.e., the local bitline will be discharged if and only if the memory cell is in a logic low state. As a result, the output of the NAND gate will be conditionally high and the global bitine will be conditionally pulled to ground by the NMOS transistor
105
. As a result, the global bitline contains the value read from the memory cell.
Due to differences in physical locations of drivers, different gate and wire loads, and/or variations due to manufacturing processes, voltages and temperatures, it is possible that the timing of the local bitines and the precharge signals can vary. Therefore, under some circumstances, PMOS transistor
104
and NMOS transistor
105
can both be active at the same time and a current, known as a crowbar current, can flow from V
DD
, through PMOS transistor
104
and NMOS transistor
105
, to ground. In addition to wasting power and generating heat, this crowbar current can also result in electro-migration related reliability issues.
A prior art bitline read circuit that eliminates the above-discussed crowbar current is shown in FIG.
2
. This read circuit is similar to the circuit shown in
FIG. 1
, except that an n-type metal oxide semiconductor (NMOS) transistor is placed in series with NMOS transistor
205
. Because PMOS transistor
204
and NMOS transistor
206
are never both activated, the crowbar current is eliminated.
Even though the read circuit shown in
FIG. 2
eliminates the crowbar current, the read circuit is not optimal. First, the size of the read circuit shown in
FIG. 2
is larger than the read circuit shown in FIG.
1
. In order to maintain the same performance, the size of the NMOS transistor
205
and the NAND
201
must be increased. Also, because the NMOS transistor
206
must rapidly pull down the global bitline, which may be highly loaded, its size must be significant. Second, the addition of the NMOS transistor
206
in the read circuit shown in
FIG. 2
increases the loading of the precharge line.
Thus, a need exists for an improved read circuit.
3. SUMMARY OF THE INVENTION
One embodiment of the invention is a circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
Another embodiment of the invention is a read circuit on a semiconductor. The read circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline; a first delay element, the input of the first delay element coupled to the precharge input; a second delay element, the input of the second delay element coupled to the output of the first delay element; a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline; a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source; a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground; a fifth switch, the gate of the fifth switch coupled to the bitline, the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.
In still another embodiment, the above read circuit includes: a seventh switch, the gate of the seventh switch coupled to the global bitline, the drain of the seventh switch coupled to the gate of the sixth switch, the source of the seventh switch coupled to ground; and an eighth switch, the gate of the eighth switch coupled to the gate of the sixth switch, the source of the eighth switch coupled to the voltage source, the drain of the eighth switch coupled to the local bitline.
In still another embodiment, the read circuit described in the preceding paragraph includes: a ninth switch, the gate of the ninth switch coupled to the precharge input, the source of the ninth switch coupled to the voltage source, the drain of the ninth switch coupled to the second local bitline; a tenth switch, the gate of the tenth switch coupled to the gate of the sixth switch, the source of the tenth switch coupled to the voltage source, the drain of the tenth switch coupled to the second local bitline; and an eleventh switch, the gate of the eleventh switch coupled to the second local bitline, the source of the eleventh switch coupled to the drain of the third switch, the drain of the eleventh switch is coupled to the gate of the sixth switch.
Still another embodiment of the invention is a

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