Memory precharge technique

Details Memory precharge technique Memory precharge technique

1994-03-29

1995-05-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365204, G11C 700

Patent

active

054126061

ABSTRACT:
An integrated circuit memory array includes column conductors that are precharged during a precharge period in order to reduce the effects of power supply voltage variations, a load resistor is connected between the column conductors and ground during a portion of the precharge period. In this manner, a voltage-divider is formed that provides a discharge path which prevents over-charging of the column conductors. An increase in power supply noise immunity is gained, thereby avoiding degradation of the worst-case memory access time that could otherwise occurs.

REFERENCES:
patent: 3848236 (1974-11-01), Troutman
patent: 4679172 (1987-07-01), Kirsch et al.
patent: 4903238 (1990-02-01), Miyatake et al.
patent: 4905197 (1990-02-01), Urai
patent: 4914633 (1990-04-01), Rose et al.

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