Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-01-25
2011-01-25
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S738000, C714S742000, C711S147000, C703S004000, C703S013000, C703S014000, C703S015000
Reexamination Certificate
active
07877659
ABSTRACT:
Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle read-write collisions and generally avoid reloading or resources. The model provides accurate result prediction, and allows write access restrictions to be removed from sensitive memory areas, such as control areas.
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Geller Felix
Naveh Yehuda
International Business Machines - Corporation
Trimmings John P
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