Memory logic for controlling refresh operations

Details Memory logic for controlling refresh operations Memory logic for controlling refresh operations

2008-01-08

2008-01-08

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

07317648

ABSTRACT:
In a self-refresh mode, alternative refresh commands such as auto-refresh and row active commands are applied to a volatile memory device in response to stored refresh and address information to implement different refresh times for memory cells having different refresh characteristics.

REFERENCES:
patent: 5276843 (1994-01-01), Tillinghast et al.
patent: 5305317 (1994-04-01), Szczepanek
patent: 5423019 (1995-06-01), Lin
patent: 5713006 (1998-01-01), Shigeeda
patent: 6195303 (2001-02-01), Zheng
patent: 6898142 (2005-05-01), Takahashi
patent: 2002/0116592 (2002-08-01), Pio
patent: 2004/0032772 (2004-02-01), Takahashi
patent: 2005/0022065 (2005-01-01), Dixon et al.
patent: 2005/0105357 (2005-05-01), Oh
patent: 07-141864 (1995-06-01), None
patent: 2001-250378 (2001-09-01), None
patent: 1997-4445 (1997-02-01), None
patent: 1998-28895 (1999-02-01), None
English language abstract of Korea Publication No. 1997-4445.
English language abstract of Korea Publication No. 1998-28895.
English language abstract of Japanese Publication No. 07-141864.
English language abstract of Japanese Publication No. 2001-250378.

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