Memory line discharge before sensing

Details Memory line discharge before sensing Memory line discharge before sensing

2000-10-27

2003-01-14

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

C365S154000, C365S203000

Reexamination Certificate

active

06507527

ABSTRACT:

BACKGROUND
The present invention relates to a method of charging high speed lines.
As illustrated in
FIG. 1
, a memory device
100
commonly includes a memory cells
106
, a bit line decoder
102
, which are also called column decoder
102
, and a word line decoder
104
, which is also called a row decoder.
Memory cells
106
is commonly configure such that a series of memory cells form rows and columns, Each memory cell is a transistor that has a source, gate, and drain. The gates of the memory cells in the same row are connected to a common word line. The word lines are connected to a word line decoder
104
. The sources of the memory cells in a column are connected to a common source-column line that is connected with a bit line decoder
102
. The drains of the memory cells in the same column are connected to a common bitline, also called a drain-column line. The bit line
110
is connected to a bit line decoder
102
. The terms “source” and “drain” can be used interchangeably because the source and drain of a transistor can be used interchangeably.
During a read operation, a memory cell is selected by the value placed on the address lines
110
,
112
. The word line decoder
104
places a voltage on the word line that corresponds to the memory cell(s) selected by the values placed on the address lines
112
. The bit line decoder
102
places a voltage on the bitline that corresponds the memory cell(s) selected by the values placed on the address lines
110
.
Some charging circuits charge the memory array's output data lines to ground. Others charge the data lines from ground to a predetermined level. These charging circuits use often P-type transistor circuit. P-type transistors are costly and have relatively low mobility. The low mobility causes the P-type transistor to charge the line slowly.
The output of the memory device
100
is sent to a sense amplifier. The sense amplifier detects the conductive (corresponding to a “one” or “on”) or nonconductive (corresponding to a “zero” or “off”) state of the memory cell that corresponds to the selected wordline and bitline.
BRIEF SUMMARY
A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level.


REFERENCES:
patent: 5946251 (1999-08-01), Sato et al.
patent: 5986474 (1999-11-01), Chung et al.
patent: 5986923 (1999-11-01), Zhang et al.
patent: 6075729 (2000-06-01), Ohhata et al.

Affiliated with

Also associated with

Rating

Memory line discharge before sensing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory line discharge before sensing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory line discharge before sensing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3002420