Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1995-12-29
1998-10-13
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
341 67, 382246, 395309, G06F 1300
Patent
active
058227709
ABSTRACT:
A memory interfacing method for a variable-length decoder and a circuit therefor are provided. The memory interfacing circuit includes a read controller for generating a read chip-enable signal and a read address in response to a first request signal output from the variable-length decoder, generating a second request signal when the read address reaches a predetermined level, and providing the second request signal to an external memory controller which is connected to an external memory, a write controller for generating a write address and a write section signal in response to an accept signal generated by the external memory controller in response to the second request signal, and an internal memory controller which includes an internal memory, for controlling data provided from an external memory to be written according to the write address and the write section signal generated by the write controller. Accordingly, the present invention simplifies complex signal processing due to frequent memory access between a variable-length decoder and an external memory.
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Chan Eddie P.
Kim Hong C.
Samsung Electronics Co,. Ltd.
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