Memory Interface supporting access to memories using different d

Details Memory Interface supporting access to memories using different d Memory Interface supporting access to memories using different d

1997-10-23

2000-10-31

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

711219, G06F 1202

Patent

active

061417394

ABSTRACT:
A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data lengths. The memory interface (28) includes an address register (50, 52) for receiving addressing information to access the memory (12). A mode bit (80) and a high/low bit (82) in the address register (50, 52) determine the different operating modes of the memory interface (28).

REFERENCES:
patent: 4796221 (1989-01-01), Tokumitsu
patent: 5175835 (1992-12-01), Beighe et al.
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5918242 (1999-06-01), Sarma et al.
patent: 6016537 (2000-01-01), Hansen et al.

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