Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-09-15
2000-09-19
Nguyen, Hoa
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
061227625
ABSTRACT:
An integrated circuit memory interface device includes a debug controller for generating debug control signals in response to memory access control signals, and individual address and data boundary-scan registers. Each of the address and data boundary-scan registers has a predetermined number of cells which are daisy-chained from cell to cell. The address and data registers are placed between a memory device and a core logic which performs normal interface operations with respect to the devices during a normal mode. The interface device includes a test access port (TAP) controller which operates in synchronism with a test clock signal during test and debugging modes, and an instruction register. The TAP controller receives a test mode select signal and generates register control signals in response to the test clock and mode select signals. The instruction register receives a test/debug instruction via the serial boundary-scan test data input port and generates memory access control signals in response the test/debug instruction.
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Nguyen Hoa
Samsung Electronics Co,. Ltd
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