Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-01-11
2001-01-30
Nelms, David (Department: 2818)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C365S191000
Reexamination Certificate
active
06182192
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory interface device and a method for accessing memories and, in particular, for memories comprising a plurality of memory regions.
BACKGROUND OF THE INVENTION
One type of known memory device is the synchronous dynamic random access memory (SDRAM). A typical example of an SDRAM is shown in FIG.
1
. The SDRAM
2
comprises two memory banks
4
a
and
4
b.
In some known SDRAMs, four memory banks are in fact provided. Each memory bank
4
a
and
4
b
contains a plurality of rows R which are sometimes referred to as pages. Each memory bank
4
a
and
4
b
also contains a plurality of columns C which intersect the rows R. A memory location is therefore identified by the bank number, the row number and the column number. To access a given memory location (or word) a memory interface unit
6
is provided. The memory interface unit
6
receives an input
7
which provides the address of the word to be accessed. The address identifies the memory bank, row and column of the word to be accessed.
Based on the address input to the memory interface unit
6
, control signals
12
are generated which are output to a respective column control unit
8
and to a respective row control unit
10
. Each bank
4
a
and
4
b
has its own row and column control units
8
and
10
. The row and column control units
8
and
10
are sometimes referred to as row and column decoders respectively. The row control unit
10
will, in accordance with the address input to the memory interface unit, select a row R in the selected memory bank
4
a
or
4
b
. Once the row R or page has been selected (or opened), then the appropriate column C is selected by the column control unit
8
, again in accordance with the input address.
The operation to open a page or row R will generally take several cycles. Once a page or row R has been opened, any word in that page or row R can be selected in one cycle. Thus a first word at a first column C location can be accessed in one cycle and a different word in that same row R but in a different column C location can be accessed in the next cycle. Once all the required accesses in a given row R or page have been completed, the open page or row R needs to be closed. This is achieved by the row control unit
10
precharging all the rows R including the selected row in the selected memory bank
4
a
or
4
b
to a given voltage. This closing operation must be completed before another page or row in the same bank can be selected or opened. This closing operation also takes several cycles.
Reference will now be made to
FIG. 2
which shows a sequence of steps which occurs when eight words from a first selected row R in a first memory bank
4
a
are read and then eight words from a second selected row in the second memory bank
4
b
are read. As can be seen, the first six cycles A are used to open the first selected row R and read the first required word in that row of the first memory bank
4
a.
The next seven cycles B are used to read the remaining required seven words in the opened row R. The next three cycles D are required to close the first selected row R in the first bank
4
a
. The next six cycles E are used to open the second selected row R in the second memory bank
4
b
and read the first required word from that row. The next seven cycles F are required to read the other seven required words in the second selected row. The last three cycles G are required to close the second selected row R in the second memory bank
4
b.
Thus, in order to read eight words from a given row in a memory bank requires 16 cycles even though the reading operation itself only requires 8 cycles. This therefore reduces the efficiency of the memory device and increases the time required in order to complete read and write operations.
It is therefore an aim of embodiments of the present invention to reduce the number of cycles required to carry out an operation in respect of a memory having a plurality of memory regions.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a memory interface device for generating a plurality of commands for controlling a memory having first and second memory regions, only one of said memory regions being accessible at a time, each memory region comprising a plurality of rows, said device comprising: a buffer for storing a plurality of received memory requests for said memory, said memory request each including information as to the row to be accessed of said respective memory region, and said buffer arranged to provide a respective output for each memory request, each of said outputs indicating said row to be accessed for the respective memory request; a detector arranged to receive said plurality of outputs from said buffer and to detect a next different row in each of said memory regions to be subsequently selected, said detector providing an output signal indicative of said detected next different row of said memory regions; and a command provider for providing a sequence of commands in response to said received memory requests and said output signals provided by said detector for controlling said memory, said command sequence being arranged so that a row of one of the first and second memory regions is accessed while said detected next different row of the other of the first and second memory regions is being selected.
Thus, as it is possible for one memory region to be accessed whilst the other memory region is being selected or deselected, the number of cycles required to access a burst may be reduced as compared to the prior art described in relation to FIG.
1
.
Preferably, the portion of the memory regions which is selected or deselected comprises a row. A row is sometimes referred to as a page in relation to certain memory devices. When a portion of the first or second memory regions is accessed, information may be read from the respective portion. Alternatively, when a portion of the first or second memory regions is accessed, the information is written into the respective portion.
A register for storing a plurality of access requests may be provided, said access requests each including information as to the portion to be accessed and the memory region. This information may comprise address information. The register means may comprise a first-in-first-out register or may be any other suitable buffer. A detector for detecting the portion which is next to be accessed in each of the memory means may be provided. The detector may be arranged to receive from the register information as to the next portion which is to be accessed in each memory region. The detecting means may receive from the register, address information in respect of each request stored in the memory means.
A comparer may be provided for comparing the portion of a memory region which is currently selected with a portion of the memory region which is next to be accessed and outputting a signal based on the comparison.
The command provider may be arranged to process received requests in a nonsequential manner if a later request specifies the same memory location of a given memory region as an earlier request with intervening requests for said given memory region being processed after said later request. In this way, if, for example, a given page is open, a later request for that same page can be processed before a request for a different page is located. This reduces the number of times that a memory page needs to be opened and closed, thus increasing the cycle time of adjacent channels as small as possible.
According to a second aspect of the present invention, there is provided a method for accessing a memory comprising a plurality of memory regions, said method comprising the steps of: selecting a row of a first one of said memory regions; subsequently selecting or deselecting a row of a second one of said memory regions; and while the row of the second one of the memory regions is being selected or deselected, the row of the first one of the memory regions is accessed.
REFERENCES:
patent:
Galanthay Theodore E.
Iannucci Robert
Nelms David
Seed IP Law Group PLLC
STMicroelectronics Limited
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