Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
2002-07-16
2004-05-04
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S220000, C345S572000
Reexamination Certificate
active
06732252
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory interface device for writing and reading a digital signal to/from a single port memory. The present invention also relates to a memory address generation device used in such a memory interface device for generating an address in a memory.
2. Description of the Related Art
In recent years, in the field of video and sound signal processing, a great amount of data has been digitalized and digitally processed. More and more source data has been made available in multimedia formats, thereby demanding for a more sophisticated digital signal processing method. For developing such a method, improving memory-related processes is considered to be a key.
There are various video signal formats, or standards, including NTSC, PAL, HDTV, VGA and SVGA, and, at the same time, there are various types of display devices including a CRT, an LCD (liquid crystal display) and a plasma display. It is required to process digital video signals of the various formats in a single display (television) system.
A digital signal processing system using a memory is essential for converting one video signal format to another, and/or for synthesizing two or more non-synchronous video signals together. In such processes, a high-speed, real-time data processing method is required for writing and reading the video signals without a break.
Conventionally, a dual port memory such as a FIFO is used for writing and reading the video signals to/from a memory in real time. Alternatively, two single port memories are used, and the real time processing is achieved by alternately controlling the write and read operations to/from the two single port memories. In addition, special purpose memory control devices are provided for converting the video signal format and for processing a plurality of non-synchronous video signals, respectively.
Thus, processing video signals in real time requires at least two single port memories or a single dual port memory, thereby making the entire system expensive. Moreover, since usable bit width and clock frequency of the video signal are limited even when such a memory arrangement is provided, a flexible system may not be realized.
Processing video signals of different formats requires a digital signal processing system capable of processing each video signal in real time using a memory at a rate associated with the signal format. Accordingly, address control methods are also becoming more complicated.
A conventional memory control device uses special purpose hardware for calculating the memory address for each of a plurality of address pointers.
However, a conventional display (television) system which processes different video signal formats needs a number of special purpose hardwares for controlling the memory addresses in different manners in accordance with the different video signal formats, thereby tending to have a large scale circuit.
Moreover, conventionally, an additional special purpose memory is needed for a frame synchronization process for converting a video signal in a synchronous system to another video signal in a different synchronous system.
SUMMARY OF THE INVENTION
According to one aspect of this invention, a memory interface device includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
In one embodiment of the invention, the memory interface device further includes a bus width conversion circuit for converting an output bus width of the input buffer to an input bus width of the single port memory, and converting an output bus width of the single port memory to an input bus width of the output buffer.
In one embodiment of the invention, the input buffer is divided along a bit line direction and along a word line direction of the input buffer into a plurality of input areas, and the output buffer is divided along a bit line direction and along a word line direction of the output buffer into a plurality of output areas.
In one embodiment of the invention, each of the input buffer and the output buffer outputs to the control section a request signal for accessing the single port memory. The control section has an arbitration circuit for prioritizing access request signals based on a predetermined priority sequence.
In one embodiment of the invention, the memory interface device further includes a circuit for writing a signal from the input buffer directly to the output buffer.
According to another aspect of this invention, a memory address generation device for generating a plurality of addresses for accessing a memory is provided. The device includes: an address update section for updating N addresses (where N is a natural number) at a predetermined timing based on a predetermined relationship among the N addresses. The updated addresses are incremented.
In one embodiment of the invention, the predetermined relationship among the N addresses is represented by K predetermined values (where K is a natural number). The address update section updates at least one of the N addresses using the K predetermined values.
In one embodiment of the invention, the K predetermined values are offset values. The address update section selectively updates one of the N addresses to obtain a reference address, and updates each remaining one-of the N addresses through a calculation based on the reference address and one of the offset values.
In one embodiment of the invention, the address update section updates the one of the N addresses to be the reference address in one direction and updates each remaining one of the N addresses in an opposite direction.
In one embodiment of the invention, a first synchronous signal and a second synchronous signal which have different frequencies are provided. The address update section updates the N addresses by selectively using the first synchronous signal or the second synchronous signal.
In one embodiment of the invention, the address update section logically divides a memory address space into a plurality of areas. The address update section generates an address by independently incrementing an address pointer in each of the areas.
In one embodiment of the invention, the memory address space starts from a start address and ends with an end address. The address update section logically divides the memory address space by a boundary into a first area including the start address and a second area including the end address. The address update section calculates an address using a logical address based on the start address either in the first area or in the second area. The address update section inverts the calculated address for the second area, thereby providing an actual address in the second area.
In one embodiment of the invention, M first synchronous system signals and K second synchronous system signals which are not synchronized with the M first synchronous signals are provided. The address update section provides a special memory area in the memory address space for storing the second synchronous system signals. The address update section calculates a read address of the second synchronous system signal based on a write address of the second synchronous system signal and the second synchronous system signal.
Thus, it is not necessary to provide a number of arithmetic units corresponding to the number of address pointers used. Rather, the addre
Adachi Kenya
Akiyama Tsuyoshi
Miki Yoichiro
Miyaguchi Hiroshi
Ninomiya Kazuki
Matsushita Electric - Industrial Co., Ltd.
Padmanabhan Mano
RatnerPrestia
Vital Pierre M.
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