Memory interface circuit and memory system including the same

Details Memory interface circuit and memory system including the same Memory interface circuit and memory system including the same

2011-08-30

2011-08-30

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S233100

Reexamination Certificate

active

08009490

ABSTRACT:
The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.

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